zephyr/arch/xtensa/soc/intel_s1000/CMakeLists.txt

zephyr_library()
zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
zephyr_library_sources(soc.c)
xtensa: intel_s1000: implement interrupt mechanism intel_s1000 has multiple levels of interrupts consisting of core, CAVS Logic and designware interrupt controller. This patchset modifies the regular gen_isr mechanism to support these multiple levels. Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com> 2017-10-12 21:02:23 +08:00			`zephyr_library()`
			`zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)`
			`zephyr_library_sources(soc.c)`