2 Commits

Author	SHA1	Message	Date
Rajavardhan Gundi	dadf9e7a81	xtensa: intel_s1000: implement interrupt mechanism ... intel_s1000 has multiple levels of interrupts consisting of core, CAVS Logic and designware interrupt controller. This patchset modifies the regular gen_isr mechanism to support these multiple levels. Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>	2018-05-01 16:46:41 -04:00
Rajavardhan Gundi	f14d1be67f	intel_s1000: Add intel_s1000 SoC ... intel_s1000 is an SoC having cavs21_LX6HiFi3_RF3_WB16 as the CPU which belongs to Xtensa family. This is being used in intel_s1000_crb. Change-Id: Ic424aa77557bf31024ddbf3f1d76b72a4adb8f66 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>	2018-05-01 16:46:41 -04:00