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zephyr/dts/riscv/neorv32.dtsi

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soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
/*
* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <skeleton.dtsi>
dts: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all dts code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 17:02:05 +08:00
#include <zephyr/dt-bindings/gpio/gpio.h>
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
/ {
dts: riscv: neorv32: add trng devicetree node Add devicetree node for the NEORV32 True Random Number Generator (TRNG). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-07 04:11:23 +08:00
chosen {
zephyr,entropy = &trng;
};
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "neorv32-cpu";
reg = <0>;
device_type = "cpu";
intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <1>;
#interrupt-cells = <1>;
firq: firq {
interrupt-map-mask = <0x0 0xffffffff>;
interrupt-map = <
0 0 &intc 0 16
0 1 &intc 0 17
0 2 &intc 0 18
0 3 &intc 0 19
0 4 &intc 0 20
0 5 &intc 0 21
0 6 &intc 0 22
0 7 &intc 0 23
0 8 &intc 0 24
0 9 &intc 0 25
0 10 &intc 0 26
0 11 &intc 0 27
0 12 &intc 0 28
0 13 &intc 0 29
0 14 &intc 0 30
0 15 &intc 0 31
>;
#interrupt-cells = <1>;
};
};
};
};
soc {
compatible = "simple-bus";
interrupt-parent = <&firq>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
dts: riscv: neorv32: add uart devicetree nodes Add devicetree nodes for the NEORV32 UART devices. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-24 03:44:33 +08:00
uart0: serial@ffffffa0 {
compatible = "neorv32-uart";
status = "disabled";
reg = <0xffffffa0 8>;
interrupts = <2>, <3>;
interrupt-names = "RX", "TX";
syscon = <&sysinfo>;
label = "UART_0";
};
dts: riscv: neorv32: add trng devicetree node Add devicetree node for the NEORV32 True Random Number Generator (TRNG). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-07 04:11:23 +08:00
trng: rng@ffffffb8 {
compatible = "neorv32-trng";
status = "disabled";
reg = <0xffffffb8 4>;
syscon = <&sysinfo>;
label = "TRNG";
};
dts: riscv: neorv32: add gpio nodes Add devicetree nodes for the NEORV32 GPIO device. The GPIO port is 64 bits wide, but Zephyr only supports up to 32 bit wide GPIO ports. The GPIO device is therefore handled as two Zephyr GPIO devices with a nexus devicetree node mapping pins 0 to 31 to the device handling the lower half, and pins 32 to 63 to the device handling the upper half. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-24 03:48:09 +08:00
gpio: gpio {
compatible = "simple-bus";
gpio-map-mask = <0xffffffe0 0xffffffc0>;
gpio-map-pass-thru = <0x1f 0x3f>;
gpio-map = <
0x00 0x0 &gpio_lo 0x0 0x0
0x20 0x0 &gpio_hi 0x0 0x0
>;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio_lo: gpio@ffffffc0 {
compatible = "neorv32-gpio";
status = "disabled";
reg = <0xffffffc0 4 0xffffffc8 4>;
reg-names = "input", "output";
gpio-controller;
ngpios = <32>;
syscon = <&sysinfo>;
label = "GPIO_LO";
#gpio-cells = <2>;
};
gpio_hi: gpio@ffffffc4 {
compatible = "neorv32-gpio";
status = "disabled";
reg = <0xffffffc4 4 0xffffffcc 4>;
reg-names = "input", "output";
gpio-controller;
ngpios = <32>;
syscon = <&sysinfo>;
label = "GPIO_HI";
#gpio-cells = <2>;
};
};
dts: riscv: neorv32: add uart devicetree nodes Add devicetree nodes for the NEORV32 UART devices. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-24 03:44:33 +08:00
uart1: serial@ffffffd0 {
compatible = "neorv32-uart";
status = "disabled";
reg = <0xffffffd0 8>;
interrupts = <4>, <5>;
interrupt-names = "RX", "TX";
syscon = <&sysinfo>;
label = "UART_1";
};
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-15 05:52:35 +08:00
sysinfo: syscon@ffffffe0 {
compatible = "neorv-sysinfo", "syscon";
status = "okay";
reg = <0xffffffe0 32>;
label = "SYSINFO";
};
};
};