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zephyr/tests/application_development/code_relocation/CMakeLists.txt

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tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(code_relocation)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})
arch/xtensa: Enable code relocation Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds support for the "sample_controller" SoC (used by qemu_xtensa) as demonstration. As Xtensa lacks a common linker script at the arch level, enabling it for each platform will be a piecemeal effort. This patch adds it to the `soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is set to be called "RAM", and hooks are inserted so that gen_relocate_app.py can add the relevant linker bits. Also, `tests/application_developent/code_relocation` was tweaked to support the qemu_xtensa platform. Basically, add the relevant linker script and ensure that relevant memory regions have their program header (PHDR) associated. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-10-20 03:25:12 +08:00
if (CONFIG_BOARD_QEMU_XTENSA)
set(RAM_PHDR :sram0_phdr)
set(SRAM2_PHDR :sram2_phdr)
endif()
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
# Code relocation feature
arch/xtensa: Enable code relocation Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds support for the "sample_controller" SoC (used by qemu_xtensa) as demonstration. As Xtensa lacks a common linker script at the arch level, enabling it for each platform will be a piecemeal effort. This patch adds it to the `soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is set to be called "RAM", and hooks are inserted so that gen_relocate_app.py can add the relevant linker bits. Also, `tests/application_developent/code_relocation` was tweaked to support the qemu_xtensa platform. Basically, add the relevant linker script and ensure that relevant memory regions have their program header (PHDR) associated. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-10-20 03:25:12 +08:00
zephyr_code_relocate(src/test_file1.c "SRAM2 ${SRAM2_PHDR}")
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
arch/xtensa: Enable code relocation Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds support for the "sample_controller" SoC (used by qemu_xtensa) as demonstration. As Xtensa lacks a common linker script at the arch level, enabling it for each platform will be a piecemeal effort. This patch adds it to the `soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is set to be called "RAM", and hooks are inserted so that gen_relocate_app.py can add the relevant linker bits. Also, `tests/application_developent/code_relocation` was tweaked to support the qemu_xtensa platform. Basically, add the relevant linker script and ensure that relevant memory regions have their program header (PHDR) associated. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-10-20 03:25:12 +08:00
zephyr_code_relocate(src/test_file2.c "RAM ${RAM_PHDR}")
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
arch/xtensa: Enable code relocation Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds support for the "sample_controller" SoC (used by qemu_xtensa) as demonstration. As Xtensa lacks a common linker script at the arch level, enabling it for each platform will be a piecemeal effort. This patch adds it to the `soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is set to be called "RAM", and hooks are inserted so that gen_relocate_app.py can add the relevant linker bits. Also, `tests/application_developent/code_relocation` was tweaked to support the qemu_xtensa platform. Basically, add the relevant linker script and ensure that relevant memory regions have their program header (PHDR) associated. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-10-20 03:25:12 +08:00
zephyr_code_relocate(src/test_file3.c SRAM2_LITERAL)
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
zephyr_code_relocate(src/test_file3.c SRAM2_TEXT)
arm: rename default RAM region from 'SRAM' to 'RAM' It's useful for RAMABLE_REGION to have a uniform name when CODE_DATA_RELOCATION is supported, because otherwise the build system needs to be aware of how the region name differs between architectures. Since architectures tend to prefer one of 'SRAM' or 'RAM' for that region, prefer to use 'RAM' as the more general term. Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-24 08:51:50 +08:00
zephyr_code_relocate(src/test_file3.c RAM_DATA)
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
zephyr_code_relocate(src/test_file3.c SRAM2_BSS)
arch/xtensa: Enable code relocation Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds support for the "sample_controller" SoC (used by qemu_xtensa) as demonstration. As Xtensa lacks a common linker script at the arch level, enabling it for each platform will be a piecemeal effort. This patch adds it to the `soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is set to be called "RAM", and hooks are inserted so that gen_relocate_app.py can add the relevant linker bits. Also, `tests/application_developent/code_relocation` was tweaked to support the qemu_xtensa platform. Basically, add the relevant linker script and ensure that relevant memory regions have their program header (PHDR) associated. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-10-20 03:25:12 +08:00
zephyr_code_relocate(../../../kernel/sem.c "RAM ${RAM_PHDR}")
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
if (CONFIG_RELOCATE_TO_ITCM)
zephyr_code_relocate(../../../lib/libc/minimal/source/string/string.c ITCM_TEXT)
endif()
zephyr_linker_sources(SECTIONS custom-sections.ld)