zephyr/boards/arm/96b_argonkey/96b_argonkey_defconfig

# SPDX-License-Identifier: Apache-2.0

CONFIG_ARM=y
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F412CG=y
CONFIG_CORTEX_M_SYSTICK=y

# 84MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=84000000

# enable uart driver
CONFIG_SERIAL=y

# enable pinmux
CONFIG_PINMUX=y

# enable GPIO
CONFIG_GPIO=y

# clock configuration
CONFIG_CLOCK_CONTROL=y

# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y

# PLL configuration
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32_HSE_CLOCK=16000000

# produce 84MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=84
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=8
CONFIG_CLOCK_STM32_AHB_PRESCALER=1

# APB1 clock must not exceed 50MHz limit
# APB2 clock is fixed at 42MHz to prevent known SPI/I2S bug
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=2

# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y