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zephyr/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series

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MXRT600: soc folder Add a soc folder for rt6xx family Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-06-19 03:14:37 +08:00
# i.MX RT6XX series configuration options
# Copyright (c) 2020, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_IMX_RT6XX
config SOC_SERIES
default "rt6xx"
config ROM_START_OFFSET
default 0x1200 if NXP_IMX_RT6XX_BOOT_HEADER
config NUM_IRQS
default 60
soc: RT600: Enable code relocation We need to relocate the power library to SRAM Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-04-07 03:30:35 +08:00
config PM
select CODE_DATA_RELOCATION_SRAM
MXRT600: Fix secure/non-secure definition for FLEXSPI The Flexspi memory address defines the location of the externally attached flash to the MXRT600 based board. The flexspi has two different memory spaces for secure and non-secure access that are not aligned for the Flexspi register space and the memory map address space. The normal method of handling this via the two different dts files for secure/non-secure is not able to handle this because a base address is applied uniformly across multiple reg items. Changes include: - pull flexspi out of peripherals block to allow it to be explicitly expressed in the respective secure/non-secure SOC DTS files. - move the flash size definition to the board level definition and use the size of the actual flash device found on the board. : Signed-off-by: David Leach <david.leach@nxp.com>
2021-11-09 13:35:00 +08:00
#
# The base address of the external flash comes from the FLEXSPI base
# address. The size of the flash is defined by what is populated and
# described in the board devicetree file.
#
soc: boards: arm: Refactor i.MX RT600 zephyr,flash usage Refactors the i.MX RT600 SoC series to be more consistent with the i.MX RT10xx SoC series by choosing a child node (external flash device) of the FlexSPI bus for zephyr,flash. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-05-18 08:35:10 +08:00
config FLASH_BASE_ADDRESS
MXRT600: Fix secure/non-secure definition for FLEXSPI The Flexspi memory address defines the location of the externally attached flash to the MXRT600 based board. The flexspi has two different memory spaces for secure and non-secure access that are not aligned for the Flexspi register space and the memory map address space. The normal method of handling this via the two different dts files for secure/non-secure is not able to handle this because a base address is applied uniformly across multiple reg items. Changes include: - pull flexspi out of peripherals block to allow it to be explicitly expressed in the respective secure/non-secure SOC DTS files. - move the flash size definition to the board level definition and use the size of the actual flash device found on the board. : Signed-off-by: David Leach <david.leach@nxp.com>
2021-11-09 13:35:00 +08:00
default $(dt_node_reg_addr_hex,/soc/spi@134000,1)
soc: boards: arm: Refactor i.MX RT600 zephyr,flash usage Refactors the i.MX RT600 SoC series to be more consistent with the i.MX RT10xx SoC series by choosing a child node (external flash device) of the FlexSPI bus for zephyr,flash. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2021-05-18 08:35:10 +08:00
dts: rt600: Add TRNG support Add RT6xx TRNG support to enable the entropy driver. Signed-off-by: David Leach <david.leach@nxp.com>
2021-07-09 12:37:21 +08:00
config ENTROPY_MCUX_TRNG
default y if HAS_MCUX_TRNG
depends on ENTROPY_GENERATOR
drivers: adc: add LPADC driver support to mimxrt685 platform Add LPADC support to the mimxrt685 platform. Signed-off-by: David Leach <david.leach@nxp.com>
2021-08-20 05:07:40 +08:00
config ADC_MCUX_LPADC
default y if HAS_MCUX_LPADC
depends on ADC
soc: rt6xx: Default flexspi logging to disabled RT600 uses the mcux flexspi driver, which can produce RWW hazards when calling code linked into flash (such as the logging subsystem). Disable logging in flexspi driver by default for RT600 series. Fixes #40744 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-11-30 01:54:38 +08:00
if FLASH_MCUX_FLEXSPI_XIP
# Avoid RWW hazards by defaulting logging to disabled
choice FLASH_LOG_LEVEL_CHOICE
default FLASH_LOG_LEVEL_OFF
endchoice
choice MEMC_LOG_LEVEL_CHOICE
default MEMC_LOG_LEVEL_OFF
endchoice
endif
soc: arm: nxp_imx: rt: Configure settings for TRNG IP RT platforms that support TRNG IP (rt10xx and rt6xx) need to set RNG and CSRNG to Xoroshiro and CTR_DRBG respectively instead of using TRNG as random source. Fixes: #37307 Signed-off-by: David Leach <david.leach@nxp.com>
2021-08-03 06:21:16 +08:00
#
# MBEDTLS is larger but much faster than TinyCrypt so choose wisely
#
config MBEDTLS
#config TINYCRYPT
default y if CSPRING_ENABLED
depends on ENTROPY_GENERATOR
if MBEDTLS
#
# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than
# what the ztest_thread_stack defaults to.
#
kconfig: Rename the TEST_EXTRA stack size option to align with the rest All stack sizes should end with STACK_SIZE. Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2022-02-18 00:09:09 +08:00
config TEST_EXTRA_STACK_SIZE
soc: arm: nxp_imx: rt: Configure settings for TRNG IP RT platforms that support TRNG IP (rt10xx and rt6xx) need to set RNG and CSRNG to Xoroshiro and CTR_DRBG respectively instead of using TRNG as random source. Fixes: #37307 Signed-off-by: David Leach <david.leach@nxp.com>
2021-08-03 06:21:16 +08:00
int
default 1024
endif # MBEDTLS
MXRT600: soc folder Add a soc folder for rt6xx family Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-06-19 03:14:37 +08:00
source "soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt6*"
endif # SOC_SERIES_MIMXRT6XX