OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/tests/application_development/code_relocation/testcase.yaml

29 lines
1.2 KiB
YAML
Raw Normal View History

tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
common:
tags: linker
tests:
tests.application_development.code_relocation:
filter: not CONFIG_CPU_HAS_NXP_MPU and CONFIG_MINIMAL_LIBC and dt_chosen_enabled("zephyr,itcm")
arch/riscv: support CONFIG_CODE_DATA_RELOCATION This implements support for relocating code to chosen memory regions via the `zephyr_code_relocate` CMake function for RISC-V SoCs. ARM-specific assumptions that were made by gen_relocate_app.py need to be corrected, in particular not assuming any particular name for the default RAM section (which is 'SRAM' for most ARM pltaforms) and not assuming 32-bit pointers (so the test works on RV64). Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-19 13:29:10 +08:00
arch_allow: arm
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
extra_configs:
- CONFIG_RELOCATE_TO_ITCM=y
tests.application_development.code_relocation_kinetis:
filter: CONFIG_CPU_HAS_NXP_MPU and CONFIG_MINIMAL_LIBC and dt_chosen_enabled("zephyr,itcm")
arch/riscv: support CONFIG_CODE_DATA_RELOCATION This implements support for relocating code to chosen memory regions via the `zephyr_code_relocate` CMake function for RISC-V SoCs. ARM-specific assumptions that were made by gen_relocate_app.py need to be corrected, in particular not assuming any particular name for the default RAM section (which is 'SRAM' for most ARM pltaforms) and not assuming 32-bit pointers (so the test works on RV64). Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-19 13:29:10 +08:00
arch_allow: arm
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
extra_configs:
- CONFIG_RELOCATE_TO_ITCM=y
- CONFIG_MPU_ALLOW_FLASH_WRITE=y
tests.application_development.code_relocation.no_itcm:
filter: not CONFIG_CPU_HAS_NXP_MPU and not dt_chosen_enabled("zephyr,itcm")
arch/riscv: support CONFIG_CODE_DATA_RELOCATION This implements support for relocating code to chosen memory regions via the `zephyr_code_relocate` CMake function for RISC-V SoCs. ARM-specific assumptions that were made by gen_relocate_app.py need to be corrected, in particular not assuming any particular name for the default RAM section (which is 'SRAM' for most ARM pltaforms) and not assuming 32-bit pointers (so the test works on RV64). Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-19 13:29:10 +08:00
arch_allow: arm
yamllint: fix all yamllint line-length errors Fix all line-length errors detected by yamllint: yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \ grep '(line-length)' Using a limit is set to 100 columns, not touching the commandlines in GitHub workflows (at least for now). Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-01-03 21:08:30 +08:00
extra_sections: _SRAM2_RODATA_SECTION_NAME _SRAM_TEXT_SECTION_NAME _SRAM_RODATA_SECTION_NAME
_SRAM_DATA_SECTION_NAME _CUSTOM_SECTION_NAME2
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
platform_allow: qemu_cortex_m3 mps2_an385 sam_e70_xplained
tests/samples: use integration_plaforms in more tests/samples integration_platforms help us control what get built/executed in CI and for each PR submitted. They do not filter out platforms, instead they just minimize the amount of builds/testing for a particular tests/sample. Tests still run on all supported platforms when not in integration mode. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-11-29 08:23:08 +08:00
integration_platforms:
- qemu_cortex_m3
arch/riscv: support CONFIG_CODE_DATA_RELOCATION This implements support for relocating code to chosen memory regions via the `zephyr_code_relocate` CMake function for RISC-V SoCs. ARM-specific assumptions that were made by gen_relocate_app.py need to be corrected, in particular not assuming any particular name for the default RAM section (which is 'SRAM' for most ARM pltaforms) and not assuming 32-bit pointers (so the test works on RV64). Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-19 13:29:10 +08:00
tests.application_development.code_relocation.riscv:
extra_args: CONF_FILE="prj_riscv.conf"
platform_allow: qemu_riscv32 qemu_riscv64
arch/xtensa: Enable code relocation Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds support for the "sample_controller" SoC (used by qemu_xtensa) as demonstration. As Xtensa lacks a common linker script at the arch level, enabling it for each platform will be a piecemeal effort. This patch adds it to the `soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is set to be called "RAM", and hooks are inserted so that gen_relocate_app.py can add the relevant linker bits. Also, `tests/application_developent/code_relocation` was tweaked to support the qemu_xtensa platform. Basically, add the relevant linker script and ensure that relevant memory regions have their program header (PHDR) associated. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-10-20 03:25:12 +08:00
tests.application_development.code_relocation.xtensa:
extra_args: CONF_FILE="prj_xtensa.conf"
platform_allow: qemu_xtensa