Commit Graph

5 Commits

Author SHA1 Message Date
Fabio Baltieri 7db1d17ee3 yamllint: fix all yamllint line-length errors
Fix all line-length errors detected by yamllint:

yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
  grep '(line-length)'

Using a limit is set to 100 columns, not touching the commandlines in
GitHub workflows (at least for now).

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-01-04 01:16:45 +09:00
Anas Nashif ba7d730e9b tests/samples: use integration_plaforms in more tests/samples
integration_platforms help us control what get built/executed in CI and
for each PR submitted. They do not filter out platforms, instead they
just minimize the amount of builds/testing for a particular
tests/sample.
Tests still run on all supported platforms when not in integration mode.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-11-29 16:03:23 +01:00
Ederson de Souza 8ac6f74a7d arch/xtensa: Enable code relocation
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds
support for the "sample_controller" SoC (used by qemu_xtensa) as
demonstration.

As Xtensa lacks a common linker script at the arch level, enabling it
for each platform will be a piecemeal effort. This patch adds it to the
`soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is
set to be called "RAM", and hooks are inserted so that
gen_relocate_app.py can add the relevant linker bits.

Also, `tests/application_developent/code_relocation` was tweaked to
support the qemu_xtensa platform. Basically, add the relevant linker
script and ensure that relevant memory regions have their program header
(PHDR) associated.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-11-03 10:25:07 +01:00
Peter Marheine d400b8135c arch/riscv: support CONFIG_CODE_DATA_RELOCATION
This implements support for relocating code to chosen memory regions via
the `zephyr_code_relocate` CMake function for RISC-V SoCs. ARM-specific
assumptions that were made by gen_relocate_app.py need to be corrected,
in particular not assuming any particular name for the default RAM
section (which is 'SRAM' for most ARM pltaforms) and not assuming 32-bit
pointers (so the test works on RV64).

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-24 10:08:06 +02:00
Hake Huang 45daf3b448 tests: application_development: add code_relocation test
add code relocation test case
1. customer relocation code and data test
2. memcpy relocation

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-08-01 18:09:28 +01:00