91 lines
2.5 KiB
C
91 lines
2.5 KiB
C
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/*
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* Copyright (c) 2023 Efinix Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT efinix_sapphire_uart0
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#include <zephyr/device.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/types.h>
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#define UART_IRQ DT_INST_IRQN(0)
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#define UART0_BASE_ADDR DT_INST_REG_ADDR(0)
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#define BSP_UART_DATA 0x00
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#define BSP_UART_STATUS 0x04
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#define BSP_UART_CLOCK_DIVIDER 0x08
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#define BSP_UART_FRAME_CONFIG 0x0C
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#define BSP_UART_WRITE_AVAILABILITY_MASK GENMASK(23, 16)
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#define BSP_UART_READ_OCCUPANCY_MASK GENMASK(31, 24)
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#define UART0_DATA_REG_ADDR UART0_BASE_ADDR + BSP_UART_DATA
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#define UART0_STATUS_REG_ADDR UART0_BASE_ADDR + BSP_UART_STATUS
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#define UART0_CLOCK_REG_ADDR UART0_BASE_ADDR + BSP_UART_CLOCK_DIVIDER
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#define UART0_FRAME_REG_ADDR UART0_BASE_ADDR + BSP_UART_FRAME_CONFIG
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#define UART0_SAMPLE_PER_BAUD 8
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#define UART0_PARITY 0 /* Off */
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#define UART0_STOP 0 /* 1 stop bit */
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struct uart_efinix_sapphire_config {
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uint32_t baudrate;
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};
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static void uart_efinix_sapphire_poll_out(const struct device *dev, unsigned char c)
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{
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/* uart_writeAvailability */
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while ((sys_read32(UART0_STATUS_REG_ADDR) & BSP_UART_WRITE_AVAILABILITY_MASK) == 0) {
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}
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sys_write8(c, UART0_DATA_REG_ADDR);
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}
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static int uart_efinix_sapphire_poll_in(const struct device *dev, unsigned char *c)
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{
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if ((sys_read32(UART0_STATUS_REG_ADDR) & BSP_UART_READ_OCCUPANCY_MASK) != 0) {
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*c = (unsigned char)sys_read8(UART0_DATA_REG_ADDR);
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return 0;
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}
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return -1;
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}
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static const struct uart_driver_api uart_efinix_sapphire_api = {
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.poll_in = uart_efinix_sapphire_poll_in,
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.poll_out = uart_efinix_sapphire_poll_out,
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.err_check = NULL,
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};
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static const struct uart_efinix_sapphire_config uart_efinix_sapphire_cfg_0 = {
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.baudrate = DT_INST_PROP(0, current_speed),
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};
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static int uart_efinix_sapphire_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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uint32_t prescaler = ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC /
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(uart_efinix_sapphire_cfg_0.baudrate * UART0_SAMPLE_PER_BAUD)) -
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1) &
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0xFFFFF;
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sys_write32(prescaler, UART0_CLOCK_REG_ADDR);
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/* 8 data bits, no parity, 1 stop bit */
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uint32_t frame_config = (UART0_SAMPLE_PER_BAUD - 1) | UART0_PARITY << 8 | UART0_STOP << 16;
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sys_write32(frame_config, UART0_FRAME_REG_ADDR);
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return 0;
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}
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/* Device tree instance 0 init */
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DEVICE_DT_INST_DEFINE(0, uart_efinix_sapphire_init, NULL, NULL, &uart_efinix_sapphire_cfg_0,
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PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, (void *)&uart_efinix_sapphire_api);
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