OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/drivers/interrupt_controller/Kconfig

140 lines
4.4 KiB
Plaintext
Raw Normal View History

x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
# Kconfig - interrupt controller configuration options
#
# Copyright (c) 2015 Intel Corporation
#
Change BSD-3 licenses to Apache 2 Change all the Intel and Wind River code license from BSD-3 to Apache 2. Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Allan Stephens <allan.stephens@windriver.com> Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2015-10-07 00:00:37 +08:00
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
#
Change BSD-3 licenses to Apache 2 Change all the Intel and Wind River code license from BSD-3 to Apache 2. Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Allan Stephens <allan.stephens@windriver.com> Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2015-10-07 00:00:37 +08:00
# http://www.apache.org/licenses/LICENSE-2.0
x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
#
Change BSD-3 licenses to Apache 2 Change all the Intel and Wind River code license from BSD-3 to Apache 2. Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Allan Stephens <allan.stephens@windriver.com> Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2015-10-07 00:00:37 +08:00
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
#
menu "Interrupt Controllers"
x86/bsp: move local apic driver to drivers/interrupt_controller Change-Id: I69350493c3b94d754f89fb37eaebe50a8076384b Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-06 00:11:24 +08:00
config LOAPIC
bool "LOAPIC"
default n
IOAPIC defaults to y when LOAPIC is enabled For as long as the IOAPIC and LOAPIC code is coupled (as it currently is), enabling LOAPIC must select IOAPIC to be enabled as well. If future commits separate the two, then the "select IOAPIC" can be dropped. Change-Id: Ibe7e6b86e5add19b8b3cc68ebecce760d8914c86 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-07-29 01:24:23 +08:00
select IOAPIC
kconfig: define architecture as a kconfig variable Do not depend on environment variables and use a kconfig variable for defining the architecture. In addition, remove the X86_32 variable, it just duplicates X86 for not good reason, at least until start supporting MCUs with 64bit. Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-10-09 18:20:52 +08:00
depends on X86
x86/bsp: move local apic driver to drivers/interrupt_controller Change-Id: I69350493c3b94d754f89fb37eaebe50a8076384b Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-06 00:11:24 +08:00
help
This option selects local APIC as the interrupt controller.
Create IOAPIC and LOAPIC Kconfig options Creating the IOAPIC and LOAPIC Kconfig options permits future commits to remove those settings from the relevant board.h files. Change-Id: Ie33c703f39c68d6e251d67b1c7cf75a0dd56a7e6 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-07-28 01:56:53 +08:00
config LOAPIC_BASE_ADDRESS
hex "Local APIC Base Address"
default 0xFEE00000
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
depends on LOAPIC
Create IOAPIC and LOAPIC Kconfig options Creating the IOAPIC and LOAPIC Kconfig options permits future commits to remove those settings from the relevant board.h files. Change-Id: Ie33c703f39c68d6e251d67b1c7cf75a0dd56a7e6 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-07-28 01:56:53 +08:00
help
This option specifies the base address of the Local APIC device.
loapic: handle spurious interrupts A special situation may occur when a processor raises its task priority to be greater than or equal to the level of the interrupt for which the processor INTR signal is currently being asserted. If at the time the INTA cycle is issued, the interrupt that was to be dispensed has become masked (programmed by software), the local APIC will deliver a spurious-interrupt vector. Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return without an EOI. Change-Id: I4cf4744bd6efd68b72e2c380269de4181dc80bd9 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2015-12-10 06:53:41 +08:00
config LOAPIC_SPURIOUS_VECTOR
bool "Handle LOAPIC spurious interrupts"
default n
depends on LOAPIC
help
A special situation may occur when a processor raises its task
priority to be greater than or equal to the level of the
interrupt for which the processor INTR signal is currently being
asserted. If at the time the INTA cycle is issued, the
interrupt that was to be dispensed has become masked (programmed
by software), the local APIC will deliver a spurious-interrupt
vector. Dispensing the spurious-interrupt vector does not affect
the ISR, so the handler for this vector should return without an EOI.
From x86 manual Volume 3 Section 10.9.
config LOAPIC_SPURIOUS_VECTOR_ID
int "LOAPIC spurious vector ID"
default -1
depends on LOAPIC_SPURIOUS_VECTOR
help
IDT vector to use for spurious LOAPIC interrupts. Note that some
arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF.
If this value is left at -1 the last entry in the IDT will be used.
Cosmetic: Fix whitespace in interrupt controller Kconfig Change-Id: I2eb4184189925bcfe433617286a364dc1e35100c Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-07-23 23:46:25 +08:00
config IOAPIC
Enable IO-APIC debgging Change-Id: I4f6c4400ec24d424b481703711d70bb5aff4f7e3 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-08-11 21:08:59 +08:00
bool "IO-APIC"
IOAPIC defaults to y when LOAPIC is enabled For as long as the IOAPIC and LOAPIC code is coupled (as it currently is), enabling LOAPIC must select IOAPIC to be enabled as well. If future commits separate the two, then the "select IOAPIC" can be dropped. Change-Id: Ibe7e6b86e5add19b8b3cc68ebecce760d8914c86 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-07-29 01:24:23 +08:00
default y
depends on LOAPIC
x86/bsp: move io apic driver to drivers/interrupt_controller Change-Id: I00f400e0405f526dd17cf22c703fab4a4968fce0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-06 01:48:18 +08:00
help
This option signifies that the target has an IO-APIC device. This
capability allows IO-APIC-dependent code to be included.
Enable IO-APIC debgging Change-Id: I4f6c4400ec24d424b481703711d70bb5aff4f7e3 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-08-11 21:08:59 +08:00
config IOAPIC_DEBUG
bool "IO-APIC Debugging"
default n
depends on IOAPIC
help
Enable debugging for IO-APIC driver.
Create IOAPIC and LOAPIC Kconfig options Creating the IOAPIC and LOAPIC Kconfig options permits future commits to remove those settings from the relevant board.h files. Change-Id: Ie33c703f39c68d6e251d67b1c7cf75a0dd56a7e6 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-07-28 01:56:53 +08:00
config IOAPIC_BASE_ADDRESS
hex "IO-APIC Base Address"
default 0xFEC00000
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
depends on IOAPIC
Create IOAPIC and LOAPIC Kconfig options Creating the IOAPIC and LOAPIC Kconfig options permits future commits to remove those settings from the relevant board.h files. Change-Id: Ie33c703f39c68d6e251d67b1c7cf75a0dd56a7e6 Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2015-07-28 01:56:53 +08:00
help
This option specifies the base address of the IO-APIC device.
config IOAPIC_NUM_RTES
int "Number of Redirection Table Entries available"
default 24
depends on IOAPIC
help
This option indicates the maximum number of Redirection Table Entries
(RTEs) (one per IRQ available to the IO-APIC) made available to the
kernel, regardless of the number provided by the hardware itself. For
most efficient usage of memory, it should match the number of IRQ lines
needed by devices connected to the IO-APIC.
ioapic: make init-time RTE masking optional In some cases we can either assume they are already masked at boot and save some cycles, or the IOAPIC has configuration from a prior boot stage that needs to be preserved. Change-Id: I0c71ff0f01a6ee13a3b9c9e239d5a933d6cb6542 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-23 00:46:35 +08:00
config IOAPIC_MASK_RTE
bool "Mask out RTE entries on boot"
default y
depends on IOAPIC
help
At boot, mask all IOAPIC RTEs if they may be in an undefined state.
You don't need this if the RTEs are either all guaranteed to be masked
when the OS starts up, or a previous boot stage has done some IOAPIC
configuration that needs to be preserved.
Cleanup whitespace in Kconfig files Convert leading whitespace into tabs in Kconfig files. Also replaced double spaces between config and <prompt>. Change-Id: I341c718ecf4143529b477c239bbde88e18f37062 Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-05-25 07:17:13 +08:00
config MVIC
x86: add Quark D2000 Interrupt Controller (MVIC) This module is based on the standard Local APIC and IO APIC source modules. This modules combines these modules into one source module that exports the same APIs defined by the Local APIC and IO APIC header modules. These routine have been adapted for the Quark D2000 Interrupt Controller which has a cutdown implementation of the Local APIC & IO APIC register sets. Change-Id: Ic80aa78918483663d76054ebadefa08d8a3f188a Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-07-31 18:57:00 +08:00
bool "Intel Quark D2000 Interrupt Controller (MVIC)"
default n
kconfig: define architecture as a kconfig variable Do not depend on environment variables and use a kconfig variable for defining the architecture. In addition, remove the X86_32 variable, it just duplicates X86 for not good reason, at least until start supporting MCUs with 64bit. Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-10-09 18:20:52 +08:00
depends on X86
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
select X86_FIXED_IRQ_MAPPING
x86: add Quark D2000 Interrupt Controller (MVIC) This module is based on the standard Local APIC and IO APIC source modules. This modules combines these modules into one source module that exports the same APIs defined by the Local APIC and IO APIC header modules. These routine have been adapted for the Quark D2000 Interrupt Controller which has a cutdown implementation of the Local APIC & IO APIC register sets. Change-Id: Ic80aa78918483663d76054ebadefa08d8a3f188a Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-07-31 18:57:00 +08:00
help
The MVIC (Intel Quark microcontroller D2000 Interrupt Controller) is
configured by default to support 32 external interrupt lines. Unlike the
traditional IA LAPIC/IOAPIC, the interrupt vectors in MVIC are fixed and
not programmable. In addition, the priorities of these interrupt
lines are also fixed.
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
config MVIC_TIMER_IRQ
int "IRQ line to use for timer interrupt"
range 0 15
mvic: default to IRQ 10 instead of 0 for timer This is a better choice of default; on Mint Valley using IRQ 0 for the timer collides with the DMA Error IRQ line. Issue: ZEP-849 Change-Id: I14cb60fbe548488198813b2351e0ed1f07c2d07d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-13 00:39:01 +08:00
default 10
x86: declare internal API for interrupt controllers Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-08-03 03:05:08 +08:00
depends on MVIC
help
Specify the IRQ line to use for the timer interrupt. This should be
an IRQ line unused by any hardware. If nested interrupts are enabled,
higher interrupt lines have priority.
arc: move interrupt controller to drivers/ Change-Id: I731c99062f4b5d2d4d1eb6a3c546ed5f3e494fa4 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-06-20 21:26:06 +08:00
config ARCV2_INTERRUPT_UNIT
bool "ARCv2 Interrupt Unit"
default y
depends on ARC
help
The ARCv2 interrupt unit has 16 allocated exceptions associated with
vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
The interrupt unit is optional in the ARCv2-based processors. When
building a processor, you can configure the processor to include an
interrupt unit. The ARCv2 interrupt unit is highly programmable.
interupt_controller/stm32_exti: driver for STM32 EXTI controller Introcuce a driver for External Interrupt/Event Controller (EXTI) found on STM32 MCUs. Change-Id: Ib206521fcc51b5dfaaf5dea9d436f8304f3a36be Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
2016-03-14 23:29:46 +08:00
source "drivers/interrupt_controller/Kconfig.stm32"
x86/bsp: move PIC (i8259) driver to drivers/interrupt_controller Change-Id: I383424667f291ad4985781a7e6566c01c76ba5e0 Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
2015-06-15 21:20:24 +08:00
endmenu