2015-06-15 21:20:24 +08:00
|
|
|
# Kconfig - interrupt controller configuration options
|
|
|
|
|
|
|
|
|
|
#
|
|
|
|
|
# Copyright (c) 2015 Intel Corporation
|
|
|
|
|
#
|
2015-10-07 00:00:37 +08:00
|
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
|
|
|
# you may not use this file except in compliance with the License.
|
|
|
|
|
# You may obtain a copy of the License at
|
2015-06-15 21:20:24 +08:00
|
|
|
#
|
2015-10-07 00:00:37 +08:00
|
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
2015-06-15 21:20:24 +08:00
|
|
|
#
|
2015-10-07 00:00:37 +08:00
|
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
|
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
|
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
|
|
|
# See the License for the specific language governing permissions and
|
|
|
|
|
# limitations under the License.
|
2015-06-15 21:20:24 +08:00
|
|
|
#
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
menu "Interrupt Controllers"
|
|
|
|
|
|
2015-06-06 00:11:24 +08:00
|
|
|
config LOAPIC
|
|
|
|
|
bool "LOAPIC"
|
|
|
|
|
default n
|
2015-07-29 01:24:23 +08:00
|
|
|
select IOAPIC
|
2015-10-09 18:20:52 +08:00
|
|
|
depends on X86
|
2015-06-06 00:11:24 +08:00
|
|
|
help
|
|
|
|
|
This option selects local APIC as the interrupt controller.
|
|
|
|
|
|
2015-09-07 20:25:45 +08:00
|
|
|
config LOAPIC_DEBUG
|
|
|
|
|
bool "LOAPIC Debug"
|
|
|
|
|
default n
|
|
|
|
|
depends on LOAPIC
|
|
|
|
|
help
|
|
|
|
|
This option enable debugging for the LOAPIC driver.
|
|
|
|
|
|
2015-07-28 01:56:53 +08:00
|
|
|
config LOAPIC_BASE_ADDRESS
|
|
|
|
|
hex "Local APIC Base Address"
|
|
|
|
|
default 0xFEE00000
|
2015-07-31 18:57:00 +08:00
|
|
|
depends on LOAPIC || MVIC
|
2015-07-28 01:56:53 +08:00
|
|
|
help
|
|
|
|
|
This option specifies the base address of the Local APIC device.
|
|
|
|
|
|
2015-07-23 23:46:25 +08:00
|
|
|
config IOAPIC
|
2015-08-11 21:08:59 +08:00
|
|
|
bool "IO-APIC"
|
2015-07-29 01:24:23 +08:00
|
|
|
default y
|
|
|
|
|
depends on LOAPIC
|
2015-06-06 01:48:18 +08:00
|
|
|
help
|
|
|
|
|
This option signifies that the target has an IO-APIC device. This
|
|
|
|
|
capability allows IO-APIC-dependent code to be included.
|
|
|
|
|
|
2015-08-11 21:08:59 +08:00
|
|
|
config IOAPIC_DEBUG
|
|
|
|
|
bool "IO-APIC Debugging"
|
|
|
|
|
default n
|
|
|
|
|
depends on IOAPIC
|
|
|
|
|
help
|
|
|
|
|
Enable debugging for IO-APIC driver.
|
|
|
|
|
|
2015-07-28 01:56:53 +08:00
|
|
|
config IOAPIC_BASE_ADDRESS
|
|
|
|
|
hex "IO-APIC Base Address"
|
|
|
|
|
default 0xFEC00000
|
2015-07-31 18:57:00 +08:00
|
|
|
depends on IOAPIC || MVIC
|
2015-07-28 01:56:53 +08:00
|
|
|
help
|
|
|
|
|
This option specifies the base address of the IO-APIC device.
|
|
|
|
|
|
|
|
|
|
config IOAPIC_NUM_RTES
|
|
|
|
|
int "Number of Redirection Table Entries available"
|
|
|
|
|
default 24
|
|
|
|
|
depends on IOAPIC
|
|
|
|
|
help
|
|
|
|
|
This option indicates the maximum number of Redirection Table Entries
|
|
|
|
|
(RTEs) (one per IRQ available to the IO-APIC) made available to the
|
|
|
|
|
kernel, regardless of the number provided by the hardware itself. For
|
|
|
|
|
most efficient usage of memory, it should match the number of IRQ lines
|
|
|
|
|
needed by devices connected to the IO-APIC.
|
|
|
|
|
|
2015-07-31 18:57:00 +08:00
|
|
|
config MVIC
|
|
|
|
|
bool "Intel Quark D2000 Interrupt Controller (MVIC)"
|
|
|
|
|
default n
|
2015-10-09 18:20:52 +08:00
|
|
|
depends on X86
|
2015-07-31 18:57:00 +08:00
|
|
|
help
|
|
|
|
|
The MVIC (Intel Quark microcontroller D2000 Interrupt Controller) is
|
|
|
|
|
configured by default to support 32 external interrupt lines. Unlike the
|
|
|
|
|
traditional IA LAPIC/IOAPIC, the interrupt vectors in MVIC are fixed and
|
|
|
|
|
not programmable. In addition, the priorities of these interrupt
|
|
|
|
|
lines are also fixed.
|
|
|
|
|
|
2015-06-20 21:26:06 +08:00
|
|
|
config ARCV2_INTERRUPT_UNIT
|
|
|
|
|
bool "ARCv2 Interrupt Unit"
|
|
|
|
|
default y
|
|
|
|
|
depends on ARC
|
|
|
|
|
help
|
|
|
|
|
The ARCv2 interrupt unit has 16 allocated exceptions associated with
|
|
|
|
|
vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
|
|
|
|
|
The interrupt unit is optional in the ARCv2-based processors. When
|
|
|
|
|
building a processor, you can configure the processor to include an
|
|
|
|
|
interrupt unit. The ARCv2 interrupt unit is highly programmable.
|
2015-06-15 21:20:24 +08:00
|
|
|
endmenu
|
