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zephyr/include/drivers/timer/arm_arch_timer.h

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drivers: timer: Add per-core ARM architected timer ARM cores may have a per-core architected timer, which provides per-cpu timers, attached to a GIC to deliver its per-processor interrupts via PPIs. This is the most common case supported by QEMU in the virt platform. This patch introduces support for this timer abstracting the way the timer registers are actually accessed. This is needed because different architectures (for example ARMv7-R vs ARMv8-A) use different registers and even the same architecture (ARMv8-A) can actually use different timers (ELx physical timers vs ELx virtual timers). So we introduce the common driver here but the actual SoC / architecture / board must provide the three helpers (arm_arch_timer_set_compare(), arm_arch_timer_toggle(), arm_arch_timer_count()) using an header file imported through the arch/cpu.h header file. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2019-10-28 00:12:58 +08:00
/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_TIMER_ARM_ARCH_TIMER_H_
#define ZEPHYR_INCLUDE_DRIVERS_TIMER_ARM_ARCH_TIMER_H_
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <zephyr/types.h>
drivers: timer: arm: Convert to new DTS macros Convert old style defines for IRQ numbers to using DT_IRQN and DT_INST to extract IRQ numbers. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-29 04:17:56 +08:00
#define ARM_TIMER_NODE DT_INST(0, arm_arm_timer)
#define ARM_TIMER_SECURE_IRQ DT_IRQ_BY_IDX(ARM_TIMER_NODE, 0, irq)
#define ARM_TIMER_NON_SECURE_IRQ DT_IRQ_BY_IDX(ARM_TIMER_NODE, 1, irq)
#define ARM_TIMER_VIRTUAL_IRQ DT_IRQ_BY_IDX(ARM_TIMER_NODE, 2, irq)
#define ARM_TIMER_HYP_IRQ DT_IRQ_BY_IDX(ARM_TIMER_NODE, 3, irq)
drivers: timer: Add per-core ARM architected timer ARM cores may have a per-core architected timer, which provides per-cpu timers, attached to a GIC to deliver its per-processor interrupts via PPIs. This is the most common case supported by QEMU in the virt platform. This patch introduces support for this timer abstracting the way the timer registers are actually accessed. This is needed because different architectures (for example ARMv7-R vs ARMv8-A) use different registers and even the same architecture (ARMv8-A) can actually use different timers (ELx physical timers vs ELx virtual timers). So we introduce the common driver here but the actual SoC / architecture / board must provide the three helpers (arm_arch_timer_set_compare(), arm_arch_timer_toggle(), arm_arch_timer_count()) using an header file imported through the arch/cpu.h header file. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2019-10-28 00:12:58 +08:00
drivers: timer: get ppi configuration from dt Use device tree provided configurations for arm architecture timer PPIs. This fixes issue of timer ppi not working on most hardware where edge-triggered PPI are not supported. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
2020-05-12 18:00:03 +08:00
#define ARM_TIMER_SECURE_PRIO DT_IRQ_BY_IDX(ARM_TIMER_NODE, 0,\
priority)
#define ARM_TIMER_NON_SECURE_PRIO DT_IRQ_BY_IDX(ARM_TIMER_NODE, 1,\
priority)
#define ARM_TIMER_VIRTUAL_PRIO DT_IRQ_BY_IDX(ARM_TIMER_NODE, 2,\
priority)
#define ARM_TIMER_HYP_PRIO DT_IRQ_BY_IDX(ARM_TIMER_NODE, 3,\
priority)
#define ARM_TIMER_SECURE_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_NODE, 0, flags)
#define ARM_TIMER_NON_SECURE_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_NODE, 1, flags)
#define ARM_TIMER_VIRTUAL_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_NODE, 2, flags)
#define ARM_TIMER_HYP_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_NODE, 3, flags)
drivers: timer: Add per-core ARM architected timer ARM cores may have a per-core architected timer, which provides per-cpu timers, attached to a GIC to deliver its per-processor interrupts via PPIs. This is the most common case supported by QEMU in the virt platform. This patch introduces support for this timer abstracting the way the timer registers are actually accessed. This is needed because different architectures (for example ARMv7-R vs ARMv8-A) use different registers and even the same architecture (ARMv8-A) can actually use different timers (ELx physical timers vs ELx virtual timers). So we introduce the common driver here but the actual SoC / architecture / board must provide the three helpers (arm_arch_timer_set_compare(), arm_arch_timer_toggle(), arm_arch_timer_count()) using an header file imported through the arch/cpu.h header file. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2019-10-28 00:12:58 +08:00
#endif /* ZEPHYR_INCLUDE_DRIVERS_TIMER_ARM_ARCH_TIMER_H_ */