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zephyr/include/drivers/timer/arm_arch_timer.h

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drivers: timer: Add per-core ARM architected timer ARM cores may have a per-core architected timer, which provides per-cpu timers, attached to a GIC to deliver its per-processor interrupts via PPIs. This is the most common case supported by QEMU in the virt platform. This patch introduces support for this timer abstracting the way the timer registers are actually accessed. This is needed because different architectures (for example ARMv7-R vs ARMv8-A) use different registers and even the same architecture (ARMv8-A) can actually use different timers (ELx physical timers vs ELx virtual timers). So we introduce the common driver here but the actual SoC / architecture / board must provide the three helpers (arm_arch_timer_set_compare(), arm_arch_timer_toggle(), arm_arch_timer_count()) using an header file imported through the arch/cpu.h header file. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2019-10-28 00:12:58 +08:00
/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_TIMER_ARM_ARCH_TIMER_H_
#define ZEPHYR_INCLUDE_DRIVERS_TIMER_ARM_ARCH_TIMER_H_
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <zephyr/types.h>
#define ARM_TIMER_SECURE_IRQ DT_ARM_ARM_TIMER_TIMER_IRQ_0
#define ARM_TIMER_NON_SECURE_IRQ DT_ARM_ARM_TIMER_TIMER_IRQ_1
#define ARM_TIMER_VIRTUAL_IRQ DT_ARM_ARM_TIMER_TIMER_IRQ_2
#define ARM_TIMER_HYP_IRQ DT_ARM_ARM_TIMER_TIMER_IRQ_3
#define ARM_TIMER_FLAGS IRQ_TYPE_EDGE
#endif /* ZEPHYR_INCLUDE_DRIVERS_TIMER_ARM_ARCH_TIMER_H_ */