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zephyr/soc/riscv/opentitan/soc.c

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soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
/*
* Copyright (c) 2023 Rivos Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
soc: riscv: opentitan: reduce the scope of some definitions Some definitions were only used in soc.c, there's no need to expose them in a public header like soc.h. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-16 21:58:08 +08:00
/* OpenTitan power management regs. */
soc: riscv: riscv-privilege: opentitan: Enable watchdog reset function Adds watchdog reset as a reset source at SoC init. This is achieved by: 1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog reset is enabled. 2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change. 3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the change has been processed. This patch is part of the OpenTitan watchdog (AON Timer) support patch series. It is needed to ensure that the watchdog reset functionality is enabled. Note that the timer itself is not enabled here, only the reset function. Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2023-05-10 06:37:13 +08:00
#define PWRMGR_BASE (DT_REG_ADDR(DT_NODELABEL(pwrmgr)))
soc: riscv: opentitan: reduce the scope of some definitions Some definitions were only used in soc.c, there's no need to expose them in a public header like soc.h. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-16 21:58:08 +08:00
#define PWRMGR_CFG_CDC_SYNC_REG_OFFSET 0x018
#define PWRMGR_RESET_EN_REG_OFFSET 0x02c
#define PWRMGR_RESET_EN_WDOG_SRC_MASK 0x002
/* Ibex timer registers. */
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
#define RV_TIMER_BASE (DT_REG_ADDR(DT_NODELABEL(mtimer)))
soc: riscv: opentitan: reduce the scope of some definitions Some definitions were only used in soc.c, there's no need to expose them in a public header like soc.h. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-16 21:58:08 +08:00
#define RV_TIMER_CTRL_REG_OFFSET 0x004
#define RV_TIMER_INTR_ENABLE_REG_OFFSET 0x100
#define RV_TIMER_CFG0_REG_OFFSET 0x10c
#define RV_TIMER_CFG0_PRESCALE_MASK 0xfff
#define RV_TIMER_CFG0_PRESCALE_OFFSET 0
#define RV_TIMER_CFG0_STEP_MASK 0xff
#define RV_TIMER_CFG0_STEP_OFFSET 16
#define RV_TIMER_LOWER0_OFFSET 0x110
#define RV_TIMER_COMPARE_LOWER0_OFFSET 0x118
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
init: remove the need for a dummy device pointer in SYS_INIT functions The init infrastructure, found in `init.h`, is currently used by: - `SYS_INIT`: to call functions before `main` - `DEVICE_*`: to initialize devices They are all sorted according to an initialization level + a priority. `SYS_INIT` calls are really orthogonal to devices, however, the required function signature requires a `const struct device *dev` as a first argument. The only reason for that is because the same init machinery is used by devices, so we have something like: ```c struct init_entry { int (*init)(const struct device *dev); /* only set by DEVICE_*, otherwise NULL */ const struct device *dev; } ``` As a result, we end up with such weird/ugly pattern: ```c static int my_init(const struct device *dev) { /* always NULL! add ARG_UNUSED to avoid compiler warning */ ARG_UNUSED(dev); ... } ``` This is really a result of poor internals isolation. This patch proposes a to make init entries more flexible so that they can accept sytem initialization calls like this: ```c static int my_init(void) { ... } ``` This is achieved using a union: ```c union init_function { /* for SYS_INIT, used when init_entry.dev == NULL */ int (*sys)(void); /* for DEVICE*, used when init_entry.dev != NULL */ int (*dev)(const struct device *dev); }; struct init_entry { /* stores init function (either for SYS_INIT or DEVICE*) union init_function init_fn; /* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows * to know which union entry to call. */ const struct device *dev; } ``` This solution **does not increase ROM usage**, and allows to offer clean public APIs for both SYS_INIT and DEVICE*. Note that however, init machinery keeps a coupling with devices. **NOTE**: This is a breaking change! All `SYS_INIT` functions will need to be converted to the new signature. See the script offered in the following commit. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> init: convert SYS_INIT functions to the new signature Conversion scripted using scripts/utils/migrate_sys_init.py. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> manifest: update projects for SYS_INIT changes Update modules with updated SYS_INIT calls: - hal_ti - lvgl - sof - TraceRecorderSource Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> tests: devicetree: devices: adjust test Adjust test according to the recently introduced SYS_INIT infrastructure. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> tests: kernel: threads: adjust SYS_INIT call Adjust to the new signature: int (*init_fn)(void); Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-19 15:33:44 +08:00
static int soc_opentitan_init(void)
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
{
soc: riscv: riscv-privilege: opentitan: Enable watchdog reset function Adds watchdog reset as a reset source at SoC init. This is achieved by: 1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog reset is enabled. 2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change. 3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the change has been processed. This patch is part of the OpenTitan watchdog (AON Timer) support patch series. It is needed to ensure that the watchdog reset functionality is enabled. Note that the timer itself is not enabled here, only the reset function. Signed-off-by: Tyler Ng <tkng@rivosinc.com>
2023-05-10 06:37:13 +08:00
/* Enable the watchdog reset (bit 1). */
sys_write32(2u, PWRMGR_BASE + PWRMGR_RESET_EN_REG_OFFSET);
/* Write CFG_CDC_SYNC to commit change. */
sys_write32(1u, PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET);
/* Poll CFG_CDC_SYNC register until it reads 0. */
while (sys_read32(PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET)) {
}
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
/* Initialize the Machine Timer, so it behaves as a regular one. */
sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET);
/* Enable timer interrupts. */
sys_write32(1u, RV_TIMER_BASE + RV_TIMER_INTR_ENABLE_REG_OFFSET);
return 0;
}
SYS_INIT(soc_opentitan_init, PRE_KERNEL_1, 0);