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zephyr/soc/riscv/opentitan/Kconfig.soc

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soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
# Copyright (c) 2023 Rivos Inc.
# SPDX-License-Identifier: Apache-2.0
soc: riscv: opentitan: reorganize SoC folder Remove from riscv-privileged, and create a standalone SoC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-04 00:30:23 +08:00
config SOC_OPENTITAN
soc: riscv: riscv-privilege: Add support for OpenTitan SOC Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-14 07:18:32 +08:00
bool "OpenTitan implementation"
select ATOMIC_OPERATIONS_C
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_ISA_EXT_ZBA
select RISCV_ISA_EXT_ZBB
select RISCV_ISA_EXT_ZBC
select RISCV_ISA_EXT_ZBS
soc: riscv: opentitan: reorganize SoC folder Remove from riscv-privileged, and create a standalone SoC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-04 00:30:23 +08:00
select RISCV
select RISCV_PRIVILEGED
soc: riscv: make RISCV_HAS_(C|P)LIC promptless These options are meant to be selected by SoC series supporting (C|P)LIC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-16 22:55:41 +08:00
select RISCV_HAS_PLIC
soc: riscv: opentitan: reorganize SoC folder Remove from riscv-privileged, and create a standalone SoC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-04 00:30:23 +08:00
# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
select RISCV_VECTORED_MODE
select GEN_IRQ_VECTOR_TABLE