2023-05-09 17:10:05 +08:00
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/*
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* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc.h"
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#ifndef CONFIG_MCUBOOT
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2024-03-07 10:50:55 +08:00
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extern int _instruction_reserved_start;
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extern int _instruction_reserved_end;
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2023-05-30 02:42:14 +08:00
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extern int _rodata_reserved_start;
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extern int _rodata_reserved_end;
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2024-03-07 10:50:55 +08:00
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2023-05-30 02:42:14 +08:00
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extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
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2024-03-07 10:50:55 +08:00
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uint8_t cfg_cache_line_size);
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2023-05-30 02:42:14 +08:00
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extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
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uint8_t cfg_cache_line_size);
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extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num,
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uint32_t rodata_start, uint32_t rodata_end, int i_off,
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int ro_off);
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2023-05-09 17:10:05 +08:00
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extern void Cache_Enable_ICache(uint32_t autoload);
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void IRAM_ATTR esp_config_instruction_cache_mode(void)
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{
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rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE,
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CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS,
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CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
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2023-05-09 17:10:05 +08:00
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}
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void IRAM_ATTR esp_config_data_cache_mode(void)
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{
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2024-10-25 06:40:22 +08:00
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Cache_Suspend_DCache();
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2023-05-30 02:42:14 +08:00
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rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE,
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CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS,
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CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
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2023-05-30 02:42:14 +08:00
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Cache_Resume_DCache(0);
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/* Configure the Cache MMU size for instruction and rodata in flash. */
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uint32_t _instruction_size =
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(uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start;
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uint32_t cache_mmu_irom_size =
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((_instruction_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) *
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sizeof(uint32_t);
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uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start;
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uint32_t cache_mmu_drom_size =
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((_rodata_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) *
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sizeof(uint32_t);
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2023-05-30 02:42:14 +08:00
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Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
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2024-03-07 10:50:55 +08:00
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int s_instr_flash2spiram_off = 0;
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int s_rodata_flash2spiram_off = 0;
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Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t),
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cache_mmu_drom_size / sizeof(uint32_t),
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(uint32_t)&_rodata_reserved_start, (uint32_t)&_rodata_reserved_end,
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s_instr_flash2spiram_off, s_rodata_flash2spiram_off);
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2023-05-09 17:10:05 +08:00
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}
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#endif /* CONFIG_MCUBOOT */
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