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zephyr/arch/riscv32/soc/riscv-privilege/fe310/soc.h

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riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:15:59 +08:00
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file SoC configuration macros for the SiFive Freedom E310 processor
*/
#ifndef __RISCV32_FE310_SOC_H_
#define __RISCV32_FE310_SOC_H_
#include <soc_common.h>
/* PINMUX Configuration */
boards: riscv: Convert HiFive1 to DTS Adds DTS bindings for sifive,pwm0, sifive,uart0, sifive,spi0, and riscv,plic0. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-08-01 00:31:44 +08:00
#define FE310_PINMUX_0_BASE_ADDR (CONFIG_FE310_GPIO_0_BASE_ADDR + 0x38)
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:15:59 +08:00
/* PINMUX IO Hardware Functions */
#define FE310_PINMUX_IOF0 0x00
#define FE310_PINMUX_IOF1 0x01
/* PINMUX MAX PINS */
#define FE310_PINMUX_PINS 32
/* Platform Level Interrupt Controller Configuration */
boards: riscv: Convert HiFive1 to DTS Adds DTS bindings for sifive,pwm0, sifive,uart0, sifive,spi0, and riscv,plic0. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-08-01 00:31:44 +08:00
#define PLIC_PRIO_BASE_ADDR PLIC_BASE_ADDRESS
#define PLIC_IRQ_EN_BASE_ADDR (PLIC_BASE_ADDRESS + 0x2000)
#define PLIC_REG_BASE_ADDR (PLIC_BASE_ADDRESS + 0x200000)
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:15:59 +08:00
boards: riscv: Convert HiFive1 to DTS Adds DTS bindings for sifive,pwm0, sifive,uart0, sifive,spi0, and riscv,plic0. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-08-01 00:31:44 +08:00
#define PLIC_MAX_PRIORITY PLIC_RISCV_MAX_PRIORITY
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:15:59 +08:00
arch: riscv32: fe310: Always-On domain adress definition Added always-on domain address definition Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>
2018-04-05 04:11:07 +08:00
/* Clock controller. */
#define PRCI_BASE_ADDR 0x10008000
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:15:59 +08:00
/* Timer configuration */
#define RISCV_MTIME_BASE 0x0200BFF8
#define RISCV_MTIMECMP_BASE 0x02004000
arch: riscv32: fe310: Always-On domain adress definition Added always-on domain address definition Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>
2018-04-05 04:11:07 +08:00
/* Always ON Domain */
#define FE310_PMUIE 0x10000140
#define FE310_PMUCAUSE 0x10000144
#define FE310_PMUSLEEP 0x10000148
#define FE310_PMUKEY 0x1000014C
#define FE310_SLEEP_KEY_VAL 0x0051F15E
#define FE310_BACKUP_REG_BASE 0x10000080
riscv32: added support for the SiFive Freedom E310 SOC The SiFive Freedom E310 SOC follows the riscv privilege architecture specification and hence is declared within the riscv privilege SOC family. It also provides support for a riscv Platform Level Interrupt Controller (PLIC) Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-03-15 05:15:59 +08:00
/* lib-c hooks required RAM defined variables */
#define RISCV_RAM_BASE CONFIG_RISCV_RAM_BASE_ADDR
#define RISCV_RAM_SIZE CONFIG_RISCV_RAM_SIZE
#endif /* __RISCV32_FE310_SOC_H_ */