OrgZephyr/zephyr
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zephyr
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3 Commits

Author SHA1 Message Date
Nathaniel Graff 45d5d5db48 boards: riscv: Convert HiFive1 to DTS 
Adds DTS bindings for sifive,pwm0, sifive,uart0, sifive,spi0, and
riscv,plic0.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
 2018-08-13 18:35:38 -05:00
Tomasz Jurtsch 6dae38cb98 arch: riscv32: fe310: Always-On domain adress definition 
Added always-on domain address definition

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Tomasz Jurtsch <tjurtsch@antmicro.com>
 2018-04-05 08:08:08 -05:00
Jean-Paul Etienne 4ae030c7b8 riscv32: added support for the SiFive Freedom E310 SOC 
The SiFive Freedom E310 SOC follows the riscv privilege
architecture specification and hence is declared within
the riscv privilege SOC family.

It also provides support for a riscv
Platform Level Interrupt Controller (PLIC)

Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
 2017-04-02 15:15:07 +00:00