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zephyr/dts/arm/renesas/gen3/rcar_gen3_cr7.dtsi

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soc: arm: add Renesas rcar_gen3 series support Most of the Renesas RCar Gen3 based SoC contains a Cortex R7 processor. This processor has access to the same memory mapped devices than the Cortex-A5x cores. - CPU operates upto 800MHz - Can use ram area from 0x40040000 to 0x42000000 - Has 512 interrupts on GIC-400 compliant with Arm GICv2 Add support for r8a77951 as first SoC of this series which is also known as H3 ES2.0 and is present present on different boards such as Salvator and R-Car Starter Kit(H3ulcb). This first SoC definition is just enough to print Hello World in a ram console. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-13 16:38:41 +08:00
/*
* Copyright (c) 2021 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <arm/armv7-r.dtsi>
#include <dt-bindings/interrupt-controller/arm-gic.h>
dts: arm: rcar_gen3_cr7: add cmt timer and clock controller The Compare match timer can be found on Renesas RCar Gen3 soc series. It depends on clock controller to supply clock to the CMT module. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-15 23:59:06 +08:00
#include <dt-bindings/clock/renesas_rcar_cpg.h>
dts: arm: rcar: add GPIO banks 5 and 6 Renesas RCar Gen3 series have up to 8 GPIOs bank. Add bank 5 and bank 6, that is used to manage user led and switches on different demo board. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-18 17:00:17 +08:00
#include <dt-bindings/gpio/gpio.h>
dts: arm: rcar_gen3_cr7: add cmt timer and clock controller The Compare match timer can be found on Renesas RCar Gen3 soc series. It depends on clock controller to supply clock to the CMT module. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-15 23:59:06 +08:00
soc: arm: add Renesas rcar_gen3 series support Most of the Renesas RCar Gen3 based SoC contains a Cortex R7 processor. This processor has access to the same memory mapped devices than the Cortex-A5x cores. - CPU operates upto 800MHz - Can use ram area from 0x40040000 to 0x42000000 - Has 512 interrupts on GIC-400 compliant with Arm GICv2 Add support for r8a77951 as first SoC of this series which is also known as H3 ES2.0 and is present present on different boards such as Salvator and R-Car Starter Kit(H3ulcb). This first SoC definition is just enough to print Hello World in a ram console. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-13 16:38:41 +08:00
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-r7";
reg = <0>;
};
};
soc {
sram0: memory@40040000 {
compatible = "mmio-sram";
reg = <0x40040000 0x1fc0000>;
};
gic: interrupt-controller@f1110000 {
compatible = "arm,gic";
reg = <0xf1110000 0x1000>,
<0xf1120000 0x20000>,
<0xf1140000 0x20000>,
<0xf1060000 0x20000>;
interrupt-controller;
#interrupt-cells = <4>;
label = "GIC";
status = "okay";
};
dts: arm: rcar_gen3_cr7: add cmt timer and clock controller The Compare match timer can be found on Renesas RCar Gen3 soc series. It depends on clock controller to supply clock to the CMT module. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-15 23:59:06 +08:00
dts: arm: rcar: add GPIO banks 5 and 6 Renesas RCar Gen3 series have up to 8 GPIOs bank. Add bank 5 and bank 6, that is used to manage user led and switches on different demo board. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-18 17:00:17 +08:00
gpio5: gpio@e6055000 {
compatible = "renesas,rcar-gpio";
reg = <0xe6055000 0x50>;
#gpio-cells = <2>;
gpio-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&cpg CPG_MOD 907>;
status = "disabled";
label = "gpio5";
};
gpio6: gpio@e6055400 {
compatible = "renesas,rcar-gpio";
reg = <0xe6055400 0x50>;
#gpio-cells = <2>;
gpio-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&cpg CPG_MOD 906>;
status = "disabled";
label = "gpio6";
};
dts: arm: rcar_gen3_cr7: add cmt timer and clock controller The Compare match timer can be found on Renesas RCar Gen3 soc series. It depends on clock controller to supply clock to the CMT module. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-15 23:59:06 +08:00
cmt0: timer@e60f0500 {
compatible = "renesas,rcar-cmt";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 143 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_0", "irq_1";
reg = <0xe60f0500 0x1004>;
clocks = <&cpg CPG_MOD 303>;
status = "disabled";
label = "cmt0";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,rcar-cpg-mssr";
reg = <0xe6150000 0x1000>;
#clock-cells = <2>;
label = "cpg";
};
soc: arm: add Renesas rcar_gen3 series support Most of the Renesas RCar Gen3 based SoC contains a Cortex R7 processor. This processor has access to the same memory mapped devices than the Cortex-A5x cores. - CPU operates upto 800MHz - Can use ram area from 0x40040000 to 0x42000000 - Has 512 interrupts on GIC-400 compliant with Arm GICv2 Add support for r8a77951 as first SoC of this series which is also known as H3 ES2.0 and is present present on different boards such as Salvator and R-Car Starter Kit(H3ulcb). This first SoC definition is just enough to print Hello World in a ram console. Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2021-01-13 16:38:41 +08:00
};
};