89 lines
1.9 KiB
Plaintext
89 lines
1.9 KiB
Plaintext
/*
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* Copyright (c) 2021 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-r.dtsi>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/renesas_rcar_cpg.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r7";
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reg = <0>;
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};
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};
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soc {
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sram0: memory@40040000 {
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compatible = "mmio-sram";
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reg = <0x40040000 0x1fc0000>;
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};
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gic: interrupt-controller@f1110000 {
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compatible = "arm,gic";
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reg = <0xf1110000 0x1000>,
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<0xf1120000 0x20000>,
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<0xf1140000 0x20000>,
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<0xf1060000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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label = "GIC";
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status = "okay";
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,rcar-gpio";
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reg = <0xe6055000 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&cpg CPG_MOD 907>;
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status = "disabled";
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label = "gpio5";
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,rcar-gpio";
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reg = <0xe6055400 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&cpg CPG_MOD 906>;
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status = "disabled";
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label = "gpio6";
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};
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cmt0: timer@e60f0500 {
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compatible = "renesas,rcar-cmt";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1";
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reg = <0xe60f0500 0x1004>;
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clocks = <&cpg CPG_MOD 303>;
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status = "disabled";
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label = "cmt0";
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,rcar-cpg-mssr";
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reg = <0xe6150000 0x1000>;
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#clock-cells = <2>;
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label = "cpg";
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};
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};
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};
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