117 lines
5.2 KiB
Plaintext
117 lines
5.2 KiB
Plaintext
/**
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@page PWR_STOP_RTC Power Stop Mode Example
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@verbatim
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******************************************************************************
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* @file PWR/PWR_STOP_RTC/readme.txt
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* @author MCD Application Team
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* @brief Description of the Power Stop Mode using RTC example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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How to enter the Stop mode and wake up from this mode by using the RTC wakeup
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timer event connected to an interrupt.
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This event is connected to EXTI_Line22.
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LED1 is ON during RUN mode and OFF during STOP mode.
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In the associated software
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- the system clock is set to 216 MHz.
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- the Low Speed Internal (LSI) clock is used as RTC clock source by default.
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- the EXTI_Line22 connected internally to the RTC Wakeup event is configured
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to generate an interrupt on rising edge each 20s.
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- the SysTick is programmed to generate an interrupt each 1 ms.
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LED1 is ON. The system enters STOP mode after 5s and will wait for the RTC Wakeup event to be
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generated each 20s, LED1 is OFF.
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After the system woken up from STOP, the clock system is reconfigured because the default clock
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after wake up is the LSI.
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The above scenario is repeated in an infinite loop.
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- STOP Mode with RTC clocked by LSI
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===================================
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- RTC Clocked by LSI
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- Regulator in LP mode
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- VREFINT OFF with fast wakeup enabled
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- LSI as SysClk after Wake Up
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- No IWDG
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- Automatic Wakeup using RTC on LSI (after ~20s)
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@note This example can not be used in DEBUG mode, this is due to the fact
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that the Cortex-M7 core is no longer clocked during low power mode
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so debugging features are disabled.
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@note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
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the RTC clock source; in this case the Backup domain will be reset in
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order to modify the RTC Clock source, as consequence RTC registers (including
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the backup registers) and RCC_CSR register are set to their reset values.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@par Keywords
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Power, PWR, Stop mode, Interrupt, EXTI, Wakeup, Low Power, RTC, External reset, LSI,
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- PWR/PWR_STOP_RTC/Inc/stm32f7xx_conf.h HAL Configuration file
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- PWR/PWR_STOP_RTC/Inc/stm32f7xx_it.h Header for stm32f7xx_it.c
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- PWR/PWR_STOP_RTC/Inc/main.h Header file for main.c
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- PWR/PWR_STOP_RTC/Src/system_stm32f7xx.c STM32F7xx system clock configuration file
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- PWR/PWR_STOP_RTC/Src/stm32f7xx_it.c Interrupt handlers
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- PWR/PWR_STOP_RTC/Src/main.c Main program
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- PWR/PWR_STOP_RTC/Src/stm32f7xx_hal_msp.c HAL MSP module
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@par Hardware and Software environment
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- This example runs on STM32F769xx/STM32F779xx/STM32F777xx/STM32F767xx devices
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- This example has been tested with STMicroelectronics STM32F769I-EVAL
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evaluation board and can be easily tailored to any other supported device
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and development board.
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- STM32F769I-EVAL Set-up :
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- None
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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