150 lines
6.9 KiB
Plaintext
150 lines
6.9 KiB
Plaintext
/**
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@page CEC CEC_DataExchange example
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@verbatim
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******************************************************************************
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* @file CEC/CEC_DataExchange/readme.txt
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* @author MCD Application Team
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* @brief Description of the CEC Data Exchangeexample.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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How to configure and use the CEC peripheral to receive and transmit messages.
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- Hardware Description
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To use this example, two STM32F769I-EVAL boards (called Device_1 and
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Device_2) are loaded with the same software then connected through CEC lines
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/|\ In the firmware file main.h, uncomment the dedicated line to use
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/_!_\ the CEC peripheral as STM32 device_1 or STM32 device_2.
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@verbatim
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*------------------------------------------------------------------------------*
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| STM32F769I_EVAL STM32F769I_EVAL |
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| Device Address :0x01 Device Address :0x03 |
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| ____________________ ____________________ |
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| | | | | |
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| | | | | |
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| | __________ | | __________ | |
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| | | CEC |____|____CECLine______|____| CEC | | |
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| | | Device_1 | | | | Device_2 | | |
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| | |__________| | | |__________| | |
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| | | | | |
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| | O LD1 | | O LD1 | |
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| | O LD2 Joystick | | O LD2 Joystick | |
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| | O LD3 _ | | O LD3 _ | |
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| | O LD4 |_| | | O LD4 |_| | |
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| | | | | |
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| | GND O--|-----------------|--O GND | |
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| |____________________| |____________________| |
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| |
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*------------------------------------------------------------------------------**
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@endverbatim
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- Software Description
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The test unrolls as follows.
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On TX side, four possible messages can be transmitted and are indicated as
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below on the transmitting board:
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- when Tamper push-button is pressed, LED1 toggles
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- when Joystick Selection push-button is pressed, LED2 toggles
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- when Joystick UP push-button is pressed, LED3 toggles
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- when Joystick DOWN push-button is pressed, LED4 toggles
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Accordingly, the following happens on the RX side in case of successful
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reception:
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- when Tamper push-button is pressed on TX side,
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* all RX side LEDs are turned off
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- when Joystick Selection push-button is pressed on TX side, on RX side
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* LED1 and LED2 are turned on
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* LED3 and LED4 are turned off
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- when Joystick UP push-button is pressed on TX side,
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* all RX side LEDs are turned on
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- when Joystick DOWN push-button is pressed on TX side, on RX side
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* LED1 and LED2 are turned off
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* LED3 and LED4 are turned on
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In case of unsuccessful reception, LED3 is turned on.
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Practically, 2 EXTI lines (EXTI15_10 and EXTI9_5) are configured to
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generate an interrupt on each falling or rising edge.
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A specific message is then transmitted by the CEC IP
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and a LED connected to a specific MFX GPIO pin is toggled.
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- EXTI9_5 is mapped to MFX used to manage Joystick pins
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- EXTI15_10 is mapped to PC.13
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Then, on TX side,
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- when rising edge is detected on EXTI9_5-SEL joystick button, LED2 toggles
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- when falling edge is detected on EXTI15_10 and EXTI line interrupt is detected
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on PC.13, LED1 toggles
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- when falling edge is detected on EXTI9_5-UP joystick button, LED3 toggles
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- when falling edge is detected on EXTI9_5-DOWN joystick button LED4 toggles
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In this example, HCLK is configured at 216 MHz.
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@par Keywords
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Connectivity, CEC, Transmission, Reception, Joystick, Data exchange
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- CEC/CEC_DataExchange/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- CEC/CEC_DataExchange/Inc/stm32f7xx_it.h Interrupt handlers header file
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- CEC/CEC_DataExchange/Inc/main.h Header for main.c module
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- CEC/CEC_DataExchange/Src/stm32f7xx_it.c Interrupt handlers
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- CEC/CEC_DataExchange/Src/system_stm32f7xx.c STM32F7xx system source file
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- CEC/CEC_DataExchange/Src/main.c Main program
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- CEC/CEC_DataExchange/Src/stm32f7xx_hal_msp.c IP hardware resources initialization
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@par Hardware and Software environment
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- This example runs on STM32F769xx/STM32F779xx/STM32F777xx/STM32F767xx Devices.
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- This example has been tested with STM32F769I-EVAL board and can be
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easily tailored to any other supported device and development board.
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- STM32F769I-EVAL revB Set-up
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- Connect PB6 of Board1 to PB6 of Board2.
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- Connect GND between two Boards.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- in main.h, uncomment DEVICE_1 for first board, uncomment DEVICE_2 for second board
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- Rebuild all files and load your image into target memory
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- With a wire, connect GPIOB-GPIO_PIN_6 between the 2 boards
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- Connect the ground of the 2 boards
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- Run the example
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*/
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