98 lines
4.3 KiB
Plaintext
98 lines
4.3 KiB
Plaintext
/**
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@page TIM_TimeBase TIM example
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@verbatim
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******************************************************************************
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* @file Examples_LL/TIM/TIM_TimeBase/readme.txt
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* @author MCD Application Team
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* @brief Description of the TIM_TimeBase example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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Configuration of the TIM peripheral to generate a timebase. This
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example is based on the STM32F7xx TIM LL API. The peripheral initialization
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uses LL unitary service functions for optimization purposes (performance and size).
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In this example TIM1 input clock TIM1CLK is set to APB2 clock (PCLK2),
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since APB2 pre-scaler is equal to 2 and it is twice PCLK2.
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TIM1CLK = 2*PCLK2
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PCLK2 = HCLK/2
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=> TIM1CLK = SystemCoreClock (216 MHz)
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To set the TIM1 counter clock frequency to 10 KHz, the pre-scaler (PSC) is calculated as follows:
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PSC = (TIM1CLK / TIM1 counter clock) - 1
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PSC = (SystemCoreClock /10 KHz) - 1
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SystemCoreClock is set to 216 MHz for STM32F7xx Devices.
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The auto-reload (ARR) is calculated to get a time base period of 100ms,
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meaning that initial time base frequency is 10 Hz.
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ARR = (TIM1 counter clock / time base frequency) - 1
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ARR = (TIM1 counter clock / 10) - 1
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Update interrupts are enabled. Within the update interrupt service routine pin PB.0
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(connected to LED1 on board NUCLEO-F767ZI) is toggled.
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User push-button can be used to modify the time base period from 100 ms
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to 1 s in 100 ms steps. To do so, every time User push-button is pressed, the
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autoreload register (ARR) is updated. In up-counting update event is generated
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at each counter overflow (when the counter reaches the auto-reload value).
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Finally the time base frequency is calculated as follows:
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time base frequency = TIM1 counter clock /((PSC + 1)*(ARR + 1)*(RCR + 1))
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@par Keywords
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Timer, TIM, Time Base, Interrupt, Clock source
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- TIM/TIM_TimeBase/Inc/stm32f7xx_it.h Interrupt handlers header file
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- TIM/TIM_TimeBase/Inc/main.h Header for main.c module
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- TIM/TIM_TimeBase/Inc/stm32_assert.h Template file to include assert_failed function
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- TIM/TIM_TimeBase/Src/stm32f7xx_it.c Interrupt handlers
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- TIM/TIM_TimeBase/Src/main.c Main program
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- TIM/TIM_TimeBase/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F767xx devices.
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- This example has been tested with NUCLEO-F767ZI board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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