/**
@page TIM_TimeBase TIM example
@verbatim
******************************************************************************
* @file Examples_LL/TIM/TIM_TimeBase/readme.txt
* @author MCD Application Team
* @brief Description of the TIM_TimeBase example.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@endverbatim
@par Example Description
Configuration of the TIM peripheral to generate a timebase. This
example is based on the STM32F7xx TIM LL API. The peripheral initialization
uses LL unitary service functions for optimization purposes (performance and size).
In this example TIM1 input clock TIM1CLK is set to APB2 clock (PCLK2),
since APB2 pre-scaler is equal to 2 and it is twice PCLK2.
TIM1CLK = 2*PCLK2
PCLK2 = HCLK/2
=> TIM1CLK = SystemCoreClock (216 MHz)
To set the TIM1 counter clock frequency to 10 KHz, the pre-scaler (PSC) is calculated as follows:
PSC = (TIM1CLK / TIM1 counter clock) - 1
PSC = (SystemCoreClock /10 KHz) - 1
SystemCoreClock is set to 216 MHz for STM32F7xx Devices.
The auto-reload (ARR) is calculated to get a time base period of 100ms,
meaning that initial time base frequency is 10 Hz.
ARR = (TIM1 counter clock / time base frequency) - 1
ARR = (TIM1 counter clock / 10) - 1
Update interrupts are enabled. Within the update interrupt service routine pin PB.0
(connected to LED1 on board NUCLEO-F767ZI) is toggled.
User push-button can be used to modify the time base period from 100 ms
to 1 s in 100 ms steps. To do so, every time User push-button is pressed, the
autoreload register (ARR) is updated. In up-counting update event is generated
at each counter overflow (when the counter reaches the auto-reload value).
Finally the time base frequency is calculated as follows:
time base frequency = TIM1 counter clock /((PSC + 1)*(ARR + 1)*(RCR + 1))
@par Keywords
Timer, TIM, Time Base, Interrupt, Clock source
@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
<20><><A0><A0><A0>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
<0A><><A0><A0><A0><A0>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
<0A><><A0><A0><A0> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
<0A><><A0><A0><A0><A0>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
<0A><><A0><A0><A0><A0>Even though the user must manage the cache coherence for read accesses.
<0A><><A0><A0><A0><A0>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
<0A><><A0><A0><A0><A0>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
@par Directory contents
- TIM/TIM_TimeBase/Inc/stm32f7xx_it.h Interrupt handlers header file
- TIM/TIM_TimeBase/Inc/main.h Header for main.c module
- TIM/TIM_TimeBase/Inc/stm32_assert.h Template file to include assert_failed function
- TIM/TIM_TimeBase/Src/stm32f7xx_it.c Interrupt handlers
- TIM/TIM_TimeBase/Src/main.c Main program
- TIM/TIM_TimeBase/Src/system_stm32f7xx.c STM32F7xx system source file
@par Hardware and Software environment
- This example runs on STM32F767xx devices.
- This example has been tested with NUCLEO-F767ZI board and can be
easily tailored to any other supported device and development board.
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Rebuild all files and load your image into target memory
- Run the example
*/
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