115 lines
5.2 KiB
Plaintext
115 lines
5.2 KiB
Plaintext
/**
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@page WWDG_Example Window Watchdog example
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@verbatim
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******************************************************************************
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* @file WWDG/WWDG_Example/readme.txt
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* @author MCD Application Team
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* @brief Description of the Window Watchdog example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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Configuration of the HAL API to periodically update the WWDG counter and simulate a software fault that
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generates an MCU WWDG reset when a predefined time period has elapsed.
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At the beginning of the main program the HAL_Init() function is called to reset
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all the peripherals, initialize the Flash interface and the systick.
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Then the SystemClock_Config() function is used to configure the system
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clock (SYSCLK) to run at 216 MHz.
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The WWDG peripheral configuration is ensured by the HAL_WWDG_Init() function.
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This later is calling the HAL_WWDG_MspInit()function which core is implementing
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the configuration of the needed WWDG resources according to the used hardware (CLOCK,
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GPIO, DMA and NVIC). You may update this function to change WWDG configuration.
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The WWDG timeout is set to 11 ms and the refresh window is set to 120.
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The WWDG counter is refreshed each 20ms in the main program infinite loop to
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prevent a WWDG reset.
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LED2 is also toggled each 20ms indicating that the program is running.
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An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt
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on the rising edge of the signal.
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The EXTI Line is used to simulate a software failure: once the EXTI Line event
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occurs by pressing the User push-button (PC.13), the corresponding interrupt is served.
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In the ISR, a write to invalid address generates a Hardfault exception containing
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an infinite loop and preventing to return to main program (the WWDG counter is
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not refreshed).
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As a result, when the WWDG counter falls to 63, the WWDG reset occurs.
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If the WWDG reset is generated, after the system resumes from reset, LED1 is turned ON.
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If the EXTI Line event does not occur, the WWDG counter is indefinitely refreshed
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in the main program infinite loop, and there is no WWDG reset.
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LED3 is turned ON and remains ON if any error occurs.
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@note Care must be taken when using HAL_Delay(), this function provides accurate
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delay (in milliseconds) based on variable incremented in SysTick ISR. This
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implies that if HAL_Delay() is called from a peripheral ISR process, then
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the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@par Keywords
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System, WWDG, Downcounter, MCU Reset, Timeout, Software fault
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- WWDG/WWDG_Example/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- WWDG/WWDG_Example/Inc/stm32f7xx_it.h Interrupt handlers header file
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- WWDG/WWDG_Example/Inc/main.h Header for main.c module
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- WWDG/WWDG_Example/Src/stm32f7xx_it.c Interrupt handlers
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- WWDG/WWDG_Example/Src/main.c Main program
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- WWDG/WWDG_Example/Src/stm32f7xx_hal_msp.c HAL MSP file
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- WWDG/WWDG_Example/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F722xx/STM32F723xx/STM32F732xx/STM32F733xx devices.
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- This example has been tested with STM32F722ZE-Nucleo_144 board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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