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/**
@page WWDG_Example Window Watchdog example
@verbatim
******************************************************************************
* @file WWDG/WWDG_Example/readme.txt
* @author MCD Application Team
* @brief Description of the Window Watchdog example.
******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
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*
******************************************************************************
@endverbatim
@par Example Description
Configuration of the HAL API to periodically update the WWDG counter and simulate a software fault that
generates an MCU WWDG reset when a predefined time period has elapsed.
At the beginning of the main program the HAL_Init() function is called to reset
all the peripherals, initialize the Flash interface and the systick.
Then the SystemClock_Config() function is used to configure the system
clock (SYSCLK) to run at 216 MHz.
The WWDG peripheral configuration is ensured by the HAL_WWDG_Init() function.
This later is calling the HAL_WWDG_MspInit()function which core is implementing
the configuration of the needed WWDG resources according to the used hardware (CLOCK,
GPIO, DMA and NVIC). You may update this function to change WWDG configuration.
The WWDG timeout is set to 11 ms and the refresh window is set to 120.
The WWDG counter is refreshed each 20ms in the main program infinite loop to
prevent a WWDG reset.
LED2 is also toggled each 20ms indicating that the program is running.
An EXTI Line is connected to a GPIO pin, and configured to generate an interrupt
on the rising edge of the signal.
The EXTI Line is used to simulate a software failure: once the EXTI Line event
occurs by pressing the User push-button (PC.13), the corresponding interrupt is served.
In the ISR, a write to invalid address generates a Hardfault exception containing
an infinite loop and preventing to return to main program (the WWDG counter is
not refreshed).
As a result, when the WWDG counter falls to 63, the WWDG reset occurs.
If the WWDG reset is generated, after the system resumes from reset, LED1 is turned ON.
If the EXTI Line event does not occur, the WWDG counter is indefinitely refreshed
in the main program infinite loop, and there is no WWDG reset.
LED3 is turned ON and remains ON if any error occurs.
@note Care must be taken when using HAL_Delay(), this function provides accurate
delay (in milliseconds) based on variable incremented in SysTick ISR. This
implies that if HAL_Delay() is called from a peripheral ISR process, then
the SysTick interrupt must have higher priority (numerically lower)
than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
to have correct HAL operation.
@par Keywords
System, WWDG, Downcounter, MCU Reset, Timeout, Software fault
@Note<74> If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
<20> <> <EFBFBD> <EFBFBD> <EFBFBD> then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
<EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
<EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
<EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
<EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> Even though the user must manage the cache coherence for read accesses.
<EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> Please refer to the AN4838 <20> Managing memory protection unit (MPU) in STM32 MCUs<55>
<EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> <EFBFBD> Please refer to the AN4839 <20> Level 1 cache on STM32F7 Series<65>
@par Directory contents
- WWDG/WWDG_Example/Inc/stm32f7xx_hal_conf.h HAL configuration file
- WWDG/WWDG_Example/Inc/stm32f7xx_it.h Interrupt handlers header file
- WWDG/WWDG_Example/Inc/main.h Header for main.c module
- WWDG/WWDG_Example/Src/stm32f7xx_it.c Interrupt handlers
- WWDG/WWDG_Example/Src/main.c Main program
- WWDG/WWDG_Example/Src/stm32f7xx_hal_msp.c HAL MSP file
- WWDG/WWDG_Example/Src/system_stm32f7xx.c STM32F7xx system source file
@par Hardware and Software environment
- This example runs on STM32F722xx/STM32F723xx/STM32F732xx/STM32F733xx devices.
- This example has been tested with STM32F722ZE-Nucleo_144 board and can be
easily tailored to any other supported device and development board.
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Rebuild all files and load your image into target memory
- Run the example
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*/
