Huang Qi d0210c1174 riscv_tcbinfo: Fix register ordering for PC ... X0 is always 0 but still should be transfered to the client, but it don't existed in thread context, use any other register for it, and its value will be omitted by gdb client. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>		2024-07-08 21:13:25 +08:00
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include	risc-v/bl808: Add GPADC character driver	2024-07-05 13:17:02 +08:00
src	riscv_tcbinfo: Fix register ordering for PC	2024-07-08 21:13:25 +08:00
CMakeLists.txt	cmake:init RISC-V cmake qemu-rv build	2023-10-26 21:01:46 +08:00
Kconfig	arch/risc-v: Add support for SOPHGO SG2000 SoC (T-Head C906)	2024-06-17 09:41:29 +08:00