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riscv_tcbinfo: Fix register ordering for PC 

X0 is always 0 but still should be transfered to the client, but it don't existed in thread context, use any other register for it, and its value will be omitted by gdb client.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2024-07-08 17:30:42 +08:00 committed by Xiang Xiao
parent 794335abce
commit d0210c1174
1 changed files with 2 additions and 1 deletions
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3
arch/risc-v/src/common/riscv_tcbinfo.c
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@ -34,7 +34,7 @@
static const uint16_t g_reg_offs[] =
{
TCB_REG_OFF(REG_EPC_NDX),
TCB_REG_OFF(REG_EPC_NDX), /* X0, but it will be ommited by gdb client */
TCB_REG_OFF(REG_X1_NDX),
TCB_REG_OFF(REG_X2_NDX),
TCB_REG_OFF(REG_X3_NDX),
@ -66,6 +66,7 @@ static const uint16_t g_reg_offs[] =
TCB_REG_OFF(REG_X29_NDX),
TCB_REG_OFF(REG_X30_NDX),
TCB_REG_OFF(REG_X31_NDX),
TCB_REG_OFF(REG_EPC_NDX),
#if 0
# ifdef CONFIG_ARCH_FPU