Commit Graph

22412 Commits

Author SHA1 Message Date
ouyangxiangzhen 733a68002c arch/riscv: Fixed hardware timer warps-around issue
This commit fixed the issue where the hardware timer wraps around and causes the system to halt.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-09-14 00:07:13 +08:00
hujun5 908df725ad arch: use up_current_regs/up_set_current_regs replace CURRENT_REGS
reason:
1 On different architectures, we can utilize more optimized strategies
  to implement up_current_regs/up_set_current_regs.
eg. use interrupt registersor percpu registers.

code size
before
    text    data     bss     dec     hex filename
 262848   49985   63893  376726   5bf96 nuttx

after
       text    data     bss     dec     hex filename
 262844   49985   63893  376722   5bf92 nuttx

size change -4

Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
   -machine virt,virtualization=on,gic-version=3 \
   -net none -chardev stdio,id=con,mux=on -serial chardev:con \
   -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-13 23:18:58 +08:00
ligd 72bdc9d9b4 armv7/8-m: change enter_critical_section to up_irq_save
caused critical_monitor will gettime, that will caused
enter_critical_seciton recursive

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-13 23:08:00 +08:00
ligd 32f56c3c62 armv8m: support busfault forward to TEE in REE handler mode
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-13 23:08:00 +08:00
ouyangxiangzhen cb7894d644 arch/x86_64: Add ARCH_INTEL64_DISABLE_CET
Intel CET (Control-flow Enforcement Technology) is a hardware enhancement aimed at mitigating the Retpoline vulnerability, but it may impact CPU branch prediction performance. This commit added ARCH_INTEL64_DISABLE_CET, which can disable CET completely with compilation option `-fcf-protection=none`.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-09-13 17:01:24 +02:00
ouyangxiangzhen 126221df97 arch/x86_64: Add elf32 multiboot1 wrapper for NuttX binary
It was discovered that attempting to load x86-64 format ELF files with a multiboot1 header using the qemu `-kernel` command would result in an error, as multiboot1 only allows x86-32 format ELF files. To address this limitation, we have developed a simple x86_32 bootloader. This bootloader is designed to copy the `nuttx.bin` file to the designated memory address (`0x100000`) and then transfer control to NuttX by executing a jump instruction (`jmp 0x100000`).

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-09-13 21:25:51 +08:00
p-szafonimateusz 2b1da40832 arch/x86_64/intel64: fix compilation errors in intel64_oneshot_lower.c
clock_time2ticks and clock_ticks2time macros changes but this file was not update

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-09-13 21:24:39 +08:00
p-szafonimateusz d6a6a0a7cc arch/intel64/hpet: add FSB interrupts support and support for 32-bit mode
These are changes to make HPET work with ACRN hypervisor:

- FSB interrupt delivery (which works like PCI MSI)
- 32-bit mode support

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-09-13 09:28:08 -03:00
Jukka Laitinen 78d2d884d3 arch/arm64/src/imx9/imx9_lpi2c.c: Ignore spurious RX interrupts
Check remaining data count, just in case an extra RX interrupt occurs
after receiving a message

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-13 09:18:30 -03:00
p-szafonimateusz 0659b333b4 arch/x86_64/intel64: add MSI/MSI-X support
Add MSI and MSI-X support for intel64

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
2024-09-13 09:42:08 +08:00
liaoao 512a496467 riscv_mtimer: modify riscv_mtimer_current to reduce precision lost
Signed-off-by: liaoao <liaoao@xiaomi.com>
2024-09-13 08:55:00 +08:00
Jouni Ukkonen ac319ba49a arch/arm64/imx9: Add system reset controller
System reset controller to powercycle ml and media blocks
and disable power-isolation

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-09-13 08:48:34 +08:00
Jouni Ukkonen 101c2f0421 arch/arm64/imx9: Configure ENET clock
Configure ENET clock to 125MHz in clock init

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-09-13 01:50:22 +08:00
Jukka Laitinen 3f82050623 arch/arm64/src/imx9: Add config option to select TX clk direction
TX clock or ref clock can be driven either from outside (PHY / oscilator) or by the ENET block.

Typical connection with RMII PHY is that the PHY drives the refclk.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-13 01:50:22 +08:00
Jukka Laitinen 56c9cbd7af arch/arm64/src/imx9: Add register definitions for imx9 wakeupmix block control
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-13 01:50:22 +08:00
Martin Vajnar 1fa4e61230 espressif: Add Quadrature Encoder driver (using PCNT)
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
Co-authored-by: Pavel Pisa <pisa@fel.cvut.cz>
2024-09-13 01:49:28 +08:00
Jouni Ukkonen c2a300d2b0 arch/arm64/imx9: Change Kconfig logic
New configuration IMX9_HAVE_ATF_FIRMWARE introduced,
it is default on and it selects ARM64_HAVE_PSCI, when compiling
bootloader or when using bootloader that does not have atf
this shall be disabled

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-09-13 01:41:56 +08:00
ouyangxiangzhen 74df0974b2 arch/x86_64: Add ARCH_X86_64_IDLE_NOP and ARCH_X86_64_IDLE_MWAIT
Using the HLT instruction in VM usually traps into the Hypervisor and releases CPU control. This will result in real-time performance degradation. Using the NOP or MWAIT instruction for an IDLE loop can reduce energy consumption while not trapping into the Hypervisor.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
2024-09-12 18:12:12 +02:00
Jukka Laitinen 08949dec66 arch/arm64/src/imx9/imx9_lpi2c.c: Cleanups and error fixes
Clean up the interrupt-driven logic in the driver; handle error cases properly,
remove dead code and simplify logic.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-12 10:27:12 -03:00
Jukka Laitinen 9bee10f05e imx9/edma: Fix function prototypes
Change "DMACH_HANDLE *handle" into "DMACH_HANDLE handle". The DMACH_HANDLE is already
defined as "void *".

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-12 10:25:17 -03:00
Jukka Laitinen 201be401c0 arch/arm64/src/imx9/imx9_lowputc.h: Allow linking to C++ by adding extern "C"
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-12 10:24:40 -03:00
Jukka Laitinen b805b73681 arch/arm64/src/imx9/imx9_lowputc.c: Fix a some preprocessor macros
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-09-12 10:24:40 -03:00
YAMAMOTO Takashi 419da0209f esp32: retire 0001-esp32-Connect-Xtensa-Instruction-RAM1-to-Cache.patch
This file is no longer used.
2024-09-12 21:17:04 +08:00
YAMAMOTO Takashi 64804be879 arch/xtensa/src/esp32/Bootloader.mk: stop applying a local patch
From @tmedicci
https://github.com/apache/nuttx/pull/13311#issuecomment-2343486553
2024-09-12 21:17:04 +08:00
YAMAMOTO Takashi e02325a0a6 esp32: Port the bootloader patch
currently esp32 protected mode requires a patched bootloader.
it's a bit cumbersome to build the bootloader for that purpose.

this commit attempts to remove the need of the patched bootloader
by applying the changes by ourselves using esp hal.
2024-09-12 21:17:04 +08:00
ligd 6a2c03732f clock: Replace all ts and tick conversion functions
Using the ts/tick conversion functions provided in clock.h

Do this caused we want speed up the time calculation, so change:
clock_time2ticks, clock_ticks2time, clock_timespec_add,
clock_timespec_compare, clock_timespec_subtract... to MACRO

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-09-12 18:14:39 +08:00
Ville Juven 8e7c0617ff arm64/Kconfig: Make the ARM64_PA/VA_BITS a true Kconfig variable
Enforcing the default 48-bit VA for everyone also implies a 4 page table
translation system. However, if less than 40 bits are needed, a full
translation table level can be dropped, making the translations faster.

Thus, make this into a configurable option, instead of enforcing the same
address widht for everyone.
2024-09-12 17:16:20 +08:00
Stuart Ianna 779d4af3e9 arch/risc-v/src/litex: Claim all pending PLIC interrupts.
Attempt to service all interrupts pending in the PLIC's claim register. Ideally, this is more efficient than switching context for each interrupt received.
2024-09-12 15:06:04 +08:00
Stuart Ianna 29ee9aacb3 arch/risc-v/common: provide architecture specific perfmon bindings.
Provides two implementations:
 - CSR_CYCLE: Cores which implement hardware performance monitoring.
 - CSR_TIME: Uses the machine time registers.

Using the up_perf_xx bindings directory is more efficient than performing a nanosecond conversion on every gettime event.
2024-09-12 15:04:02 +08:00
Ville Juven ca4bd482a0 arm64/task/pthread_start: Fix rare issue with context register location
There is a tiny possibility that when a process is started a trap is
taken which causes a context switch. This moves the kernel stack
unexpectedly and the task start logic no longer works.

Fix this by recording the initial context location, and use that to
trampoline into the user process with interrupts disabled. This ensures
the context stays intact AND the kernel stack is fully unwound before
the user process starts.
2024-09-11 08:59:01 -03:00
Ville Juven 87d9dac817 arm64/syscall: (Re-)enable interrupts only if they were previously enabled
Don't change the CPU state unexpectedly
2024-09-11 19:51:35 +08:00
Ville Juven 498275ca43 arm64/irq: Add mask for DAIF and SPSR DAIF bits
Use them for critical section handling, removes a bit of copy&pasted
code behind CONFIG_ARM64_DECODEFIQ flag
2024-09-11 19:51:35 +08:00
Huang Qi fc5a029e44 riscv: Unify the extended context save/restore
This patch unifies the extended context save/restore for RISC-V,
allowing the customized context save/restore to be used, for example,
the extended context in rv32m1.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-09-11 19:50:07 +08:00
Ville Juven 48f545d54a arm64/crt0.c: Fix stack alignment when executing signal trampoline
The stack alignment requirement is 16-bytes, not 8-bytes.
2024-09-11 19:49:24 +08:00
Tiago Medicci Serrano f063e47c28 espressif: Update external libraries to fix GPIO interrupt bug
This commit updates the HAL version used by NuttX to fix the bug
reported in https://github.com/apache/nuttx/issues/13303
2024-09-11 09:05:45 +08:00
Ville Juven 132868b728 arm64_syscall.c: Don't need to set register context during syscall
The register context is not needed, the original idea was to provide
the user stack pointer for signal handler delivery, but the user stack
can be obtained via sp_el0 so the context registers are not needed.

SP0 is not stored upon exception entry anyways, so this code is just
completely redundant and wrong.
2024-09-10 23:23:21 +08:00
hujun5 1aab457b4c sched:add parameters to restore_critical_section
reason:
In SMP, when a context switch occurs, restore_critical_section is executed.
To reduce the time taken for context switching, we directly pass the required
parameters to restore_critical_section instead of acquiring them repeatedly.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-09-10 23:14:09 +08:00
Ville Juven 0ca1a07e84 arm64_addrenv_pgmap.c: Revoke user execution access to kernel mmap'd pages
Otherwise, user can run code from there
2024-09-10 23:10:57 +08:00
Ville Juven eebff25d69 arm64_mmu.h: Change ordering of access flags for user data
This makes it more readable, no functional changes
2024-09-10 23:05:12 +08:00
Ville Juven 080f9ede45 arm64_mmu.c: Fix kernel L1 page table size
The kernel L1 page table must be at least 1 page
2024-09-10 23:05:12 +08:00
Ville Juven 4149e45450 arm64_mmu: Fix TLBI instruction format
The vaddr field in TLBI means: Bits[55:12] of the virtual address to match.
This basically means the page offset of the virtual address, so the input
vaddr must be shifted to the page offset.

Reference TLBI VALE1IS register description from ARMv8-A reference manual.
2024-09-10 23:05:12 +08:00
Ville Juven fbc796cff1 arm64_mmu: Do not set accessed-flag for table descriptors
The 12:0 bits in table descriptors are RES0 and AF is the 10th bit, so
it is not valid to set it in this case.

Fix this by moving AF to the common MMU_MT_NORMAL_FLAGS field
2024-09-10 23:05:12 +08:00
Ville Juven 00c4da73b3 arm64_addrenv.c: Flush kernel page table copy to user mappings
Make sure the user L1 page is updated to system memory when the kernel
mappings are copied.

Also, flush the I-cache when switching address environments.
2024-09-10 22:56:06 +08:00
Ville Juven 20ce41d080 arm64_vector_table.S: Remove unnecessary instruction
The expression "sub    x0,  x0, #8 * XCPTCONTEXT_GP_REGS" is void,
as the next instruction overwrites x0 anyway.
2024-09-10 22:55:12 +08:00
shizhenghui 7472b08851 sim_sound: add AUDIOUTILS_LAME to dependency list
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-09-10 20:25:48 +08:00
shizhenghui dea9e5343d arch/sim/Makefile: add libmad & lame include path
Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-09-10 20:25:48 +08:00
shizhenghui 6637606096 sim_offload: move out of the posix directory
The libmad and libmp3lame libraries have been ported to
apps/audioutils and will be compiled with NuttX.

Signed-off-by: shizhenghui <shizhenghui@xiaomi.com>
2024-09-10 20:25:48 +08:00
cuiziwei 6eb286ae01 sim:Remove -lmad cause it has been ported to the apps/audioutils directory.
Signed-off-by: cuiziwei <cuiziwei@xiaomi.com>
2024-09-10 20:25:48 +08:00
Bowen Wang bf5c571098 arm64/qemu_boot: add arm64 pci io memory map
and rename other pci region name to make them more
readable

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-10 14:34:31 +08:00
Bowen Wang b12fa7f760 qemu_boot: change IVSHMEM memory region to PCI memory region
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
2024-09-10 14:34:31 +08:00