arm64/irq: Add mask for DAIF and SPSR DAIF bits
Use them for critical section handling, removes a bit of copy&pasted code behind CONFIG_ARM64_DECODEFIQ flag
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@ -220,6 +220,14 @@
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#define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + XCPTCONTEXT_FPU_REGS)
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#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS)
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#ifdef CONFIG_ARM64_DECODEFIQ
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# define IRQ_DAIF_MASK (3)
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#else
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# define IRQ_DAIF_MASK (2)
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#endif
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#define IRQ_SPSR_MASK (IRQ_DAIF_MASK << 6)
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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@ -349,13 +357,9 @@ static inline irqstate_t up_irq_save(void)
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__asm__ __volatile__
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(
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"mrs %0, daif\n"
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#ifdef CONFIG_ARM64_DECODEFIQ
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"msr daifset, #3\n"
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#else
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"msr daifset, #2\n"
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#endif
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"msr daifset, %1\n"
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: "=r" (flags)
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:
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: "i" (IRQ_DAIF_MASK)
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: "memory"
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);
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@ -371,13 +375,9 @@ static inline irqstate_t up_irq_enable(void)
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__asm__ __volatile__
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(
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"mrs %0, daif\n"
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#ifdef CONFIG_ARM64_DECODEFIQ
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"msr daifclr, #3\n"
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#else
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"msr daifclr, #2\n"
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#endif
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"msr daifclr, %1\n"
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: "=r" (flags)
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:
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: "i" (IRQ_DAIF_MASK)
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: "memory"
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);
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return flags;
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@ -56,22 +56,6 @@
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.endm
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.macro enable_irq
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#ifdef CONFIG_ARM64_DECODEFIQ
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msr daifclr, #3
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#else
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msr daifclr, #2
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#endif
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.endm
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.macro disable_irq
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#ifdef CONFIG_ARM64_DECODEFIQ
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msr daifset, #3
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#else
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msr daifset, #2
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#endif
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.endm
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -238,9 +222,9 @@ SECTION_FUNC(text, arm64_sync_exc)
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/* Call dispatch_syscall() on the kernel stack with interrupts enabled */
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enable_irq
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msr daifclr, #IRQ_DAIF_MASK /* Re-enable interrupts */
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bl dispatch_syscall
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disable_irq
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msr daifset, #IRQ_DAIF_MASK /* Disable interrupts */
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/* Save the return value into the user context */
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