Commit Graph

53203 Commits

Author SHA1 Message Date
Matheus Catarino c6eea4ad8b add LDC2 (dlang) support
*Note:* ldmd2 is ldc2-wrapper, allow using dmd frontend flags.
      This support may be extended to gdc (gnu) if nuttx developers demand it
  or are interested in it.
2024-06-06 09:32:56 +08:00
zhanghongyu ee4c25f34e sem_open: return error code, sem returned by parameter
pointer comparison is unsigned, when returning -errno will be converted
to a large positive number, can not enter the error handling branch,
therefore, the error code is returned directly and the sem is returned
through the parameters.

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2024-06-06 02:40:50 +08:00
Tiago Medicci Serrano 96f83bb03a net: Enable `CONFIG_NET_ARP_SEND` by default
Enable logic to send ARP requests if the target IP address mapping
does not appear in the ARP table.

Please check the comment in https://github.com/apache/nuttx/issues/12446#issuecomment-2145856778
2024-06-06 02:40:16 +08:00
Alan Carvalho de Assis f830376ef2 DOC: Add how to get application on NSH
Signed-off-by: Alan C. Assis <acassis@gmail.com>
2024-06-06 02:39:56 +08:00
zhanghongyu 9472426f69 net/inet: Rename ttl to s_ttl in sconn.
uniform naming convention

Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2024-06-05 23:22:15 +08:00
Jani Paalijarvi b32a1dfd3d risc-v/mpfs: Add error handling for PMP conf
Check return value of mpfs_board_pmp_setup() and
jump to mpfs_board_pmp_error() in case of error.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-06-05 12:07:02 -03:00
Takuya Miyashita 072890c1bf arch/arm/src/armv7-m/arm_vectors.c : Add the address alignment.
Add the address alignment to keep the constraint of ARMv7-M architecture same as RAM vector.

ARMv7-M architecture describes the vector table address alignment as following.
The Vector table must be naturally aligned to a power of two
whose alignment value is greater than or equal to (Number of Exceptions supported x 4),
with a minimum alignment of 128 bytes.

I wonder why the implementation of arm_vectors.c does not follow
this constraint of address alignment about ARMv7-M architecture.
Although RAM vector is taken care about it.

I think, as the result it was done by linker script on each board.
At our system, NuttX will be started by bootloader.
To fix the address of entry point(__start) I set the address of entry point to beginning of binary,
so the beginning of binary is not a vector table.
At this case, keeping the address alignment constraint of arm_vectors.c is needed.
2024-06-05 21:47:57 +08:00
Almir Okato 4178f3ede4 esp32s2: remove legacy bootloader support
Deprecate Legacy Boot for ESP32-S2.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-06-04 18:53:14 -03:00
Almir Okato 16f8966fa9 esp32s2: add simple boot support
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s2 targets and removes the need
for running 'make bootloader' command for it.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2024-06-04 18:53:14 -03:00
Xu Xingliang b5f8498142 mm: check double free before adding to delaylist
If free memory is delayed, check case of double free in the first
place.

Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
2024-06-04 17:42:28 -03:00
Eren Terzioglu 24af23e49c esp32[c3]: Add XTWDT support 2024-06-04 17:42:07 -03:00
Takuya Miyashita 146975d069 arch: cxd32xx: Add cxd32xx SoC support
Supported drivers
 - Serial(PL011), Timer, NVIC
2024-06-04 22:21:56 +08:00
buxiasen 95c4463618 pm: update pm_domain_register/pm_domain_unregister document
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-06-04 22:04:25 +08:00
buxiasen 1933f9648d pm: remove pm global, make per domain isolated
After change, when CONFIG_PM_NDOMAINS > 1,
the pm_register will not able to get notificaion
from not PM_IDLE_DOMAIN.
Should use pm_domain_register as a replacement.

Isolate domains from global callbacks can decrease
not necessary execution, and reduce the
lock instruction requirements.

Signed-off-by: buxiasen <buxiasen@xiaomi.com>
2024-06-04 22:04:25 +08:00
adriendesp 6f50847278 arch/xmc4 Add partial vadc support : Background request source 2024-06-04 09:42:54 -03:00
chao an a219d75ace boards/arm/lpc17xx_40xx: enlarge ksram size to 6k
Signed-off-by: chao an <anchao@lixiang.com>
2024-06-04 14:26:55 +08:00
chao an 58ad896281 sched/signal: move signal structures pool to bss
Decoupling with memory allocator

Signed-off-by: chao an <anchao@lixiang.com>
2024-06-04 14:26:55 +08:00
chao an 81c140a953 sched/mqueue: move message queue buffer to bss
Signed-off-by: chao an <anchao@lixiang.com>
2024-06-04 14:26:55 +08:00
Ville Juven 74702085f0 defconfigs: Add SCHED_HAVE_PARENT=y to configs with WAITPID && BUILD_KERNEL
The added depencendy broke some of the defconfigs
2024-06-03 18:00:40 +02:00
Ville Juven c1ceec3404 sched/Kconfig: waitpid() depends on SCHED_HAVE_PARENT if BUILD_KERNEL
waitpid() cannot be used in kernel mode unless SCHED_HAVE_PARENT is
selected -> add dependency if BUILD_KERNEL is selected.

Why? Because without SCHED_HAVE_PARENT waitpid() works in a non-standard
way, meaning it does not use SIGCHLD to wake the parent, as it should.

Also, returning the child status via stat_loc corrupts memory as stat_loc
points to the parent's address environment:

pid_t nxsched_waitpid(pid_t pid, int *stat_loc, int options)
{
  ...
  group->tg_statloc = stat_loc;
  ...
}

And later when the status is returned, the child writes to tg_statloc,
which points to the parent's address environment -> random memory
corruption:

static inline void nxtask_exitwakeup(FAR struct tcb_s *tcb, int status)
{
  ...
  if (group->tg_statloc != NULL)
    {
      *group->tg_statloc = status << 8;
    }
  ...
}
2024-06-03 18:00:40 +02:00
Ville Juven 36cafbb37f mm/gran: Fix GRAN_ALIGNED() macro
GRAN_ALIGNED should check that the memory block's alignment (log2align)
is correct, not that the memory block is aligned with the granule size.

This fixes DEBUGASSERT() in mm_granfree:
_assert: Assertion failed : at file: mm_gran/mm_granfree.c:49

The assertion triggers if granule size != alignment.
2024-06-03 22:06:38 +08:00
Stuart Ianna 39e6e25565 drivers/devicetree/fdt: add additional fdt parsing utilities.
These utilities remove some of the boilerplate needed for FDT parsing and device initialization.
2024-06-03 22:05:00 +08:00
TakuyaMiyasita d6445484fe drivers/serial/uart_pl011.c : add the bitmask according to PL011 spec. (Although almost no problem.) 2024-06-03 21:18:44 +08:00
TakuyaMiyasita c93383407b drivers/serial/uart_pl011.c : add the interface about clock and reset control for reducing power consumption. 2024-06-03 21:18:44 +08:00
TakuyaMiyasita 99dee09146 drivers/serial/uart_pl011.c : bug fix about the function : pl011_txready(). 2024-06-03 21:18:44 +08:00
SPRESENSE 937bdcec78 boards: cxd56xx: Fix read position in cxd5610 gnss driver
Add process to reset read position after read is complete
to fix NMEA output with DC report.
2024-06-03 12:41:57 +02:00
liqinhui 05b101134a net:Support jumbo frame prealloc the iob for the ICMP/UDP/TCP.
For the ICMP, UDP and TCP, pre-alloc an iob for a jumbo frame.

Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2024-06-02 09:31:37 -03:00
liqinhui 45fc68e904 sim/net: Support to set the MTU of the sim netdevice.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
2024-06-02 09:31:37 -03:00
Stuart Ianna e3056c781e arch/risc-v/riscv_mtimer: Update the mtimecmp value once per interrupt event.
Cache the next timeout value in the drivers instance and update the mtimecmp value once. This is advantageous as the opensbi ecall to set the timer is expensive in systems which don't have the supervisor mode timer extension.
2024-06-02 09:28:19 -03:00
raiden00pl 105e4f44d4 libdsp: fix gcc14 error and clean up includes 2024-06-02 09:27:36 -03:00
raiden00pl d942e373bc drivers/foc_dummy.c: fix compilation for CONFIG_MOTOR_FOC_BEMF_SENSE=y 2024-06-02 09:27:36 -03:00
raiden00pl c09f7f7864 cmake: add missing arp_acd.c file 2024-06-02 09:27:36 -03:00
raiden00pl b01e8b1b6e net/ipfrag/Kconfig: NET_IPFRAG depends on IOB_NCHAINS > 0 2024-06-02 09:27:36 -03:00
raiden00pl e062f4591c sched/task/task_exithook.c: fix gcc14 error
umm_memdump() should be always declared otherwise we get error when DEBUG_MM=n:

sched/task/task_exithook.c:468:7: error: implicit declaration of function ‘umm_memdump’; did you mean ‘mm_memdump’? [-Wimplicit-function-declaration]
2024-06-02 09:27:36 -03:00
raiden00pl 13fa50c94a cmake: fix compilation
there is no spawn/lib_task_spawn. file
2024-06-02 09:27:36 -03:00
raiden00pl 37b3dc11a5 Kconfig: move LTO options to Build Setup menu
LTO is optimization option so it's more appropriate to place it
in the same place as other optimization options
2024-06-02 09:26:35 -03:00
Ville Juven e6973c764c riscv/syscall: Optimize user service call performance
This patch changes how user service calls are executed:
Instead of using the common interrupt logic, execute the user service
call directly.

Why? When a user makes a service call request, all of the service call
parameters are already loaded into the correct registers, thus it makes
no sense to first clobber them and then reload them, which is what the
old logic does. It is much more effective to run the system call directly.

During a user system call the interrupts must be re-enabled, which the
new logic does as soon as we know the exception is a user service call
request.

This patch does NOT change the behavior of reserved system calls (like
switch_context), only the user service call request is affected.
2024-06-01 10:40:53 -03:00
Ville Juven a5574d9485 risc-v_percpu: Add TCB to the per CPU structure
Also, convert the type to union; we don't need the list element once
the item has been popped from the free list (the linkage is never needed
when the item is in use).
2024-06-01 10:40:53 -03:00
Ville Juven 6bad48e4c7 riscv_syscall.S: Remove duplicated code
Return from exception is common code for both system calls and
exceptions
2024-06-01 10:40:53 -03:00
raiden00pl 394de18316 netfilter/ip_tables.h: fix gcc14 error
/home/raiden00/git/RTOS/nuttx/nuttx/include/nuttx/net/netfilter/ip_tables.h:281:24: error: returning 'char *' from a function with incompatible return type 'struct xt_entry_target *' [-Wincompatible-pointer-types]
  281 |   return (FAR char *)e + e->target_offset;
      |          ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~
2024-05-31 18:14:11 -03:00
raiden00pl 3ce9e34ec9 include/crypto/curve25519.h: fix gcc14 error
/home/raiden00/git/RTOS/nuttx/nuttx/include/crypto/curve25519.h:42:5: error: implicit declaration of function 'arc4random_buf' [-Wimplicit-function-declaration]
   42 |     arc4random_buf(secret, CURVE25519_KEY_SIZE);
2024-05-31 18:14:11 -03:00
anjiahao 3312ab2087 gdbstub:fix get thread rsp command crash
riscv-gdb/gdb/thread.c:1309: internal-error: void switch_to_thread(thread_info*): Assertion `thr != NULL' failed.

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2024-05-31 23:19:18 +08:00
Jouni Ukkonen a5cd1cf89b imx9: map flexspi peripheral interface
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-05-31 10:22:27 +08:00
Jouni Ukkonen 8382916d26 Map iMX93 OCRAM memory to mmu
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-05-31 10:22:27 +08:00
Jouni Ukkonen e8de8cf60a Add S3MUA base address for Security Enclave
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-05-31 10:22:27 +08:00
Stuart Ianna 1f02c05c6d arch/litex/litex_arch_alarm: Support tickless schedular with arch alarm.
This provides an alternate tickless scheduling method, which uses the riscv
mtimer as a timebase, allowing the time and timeh registers to used
throughout an application.

The exiting tickless method, using Litex's timer0 has been left in place, as
it is a more performant option, but currently has the potential issue
identified in #11189.
2024-05-31 10:21:44 +08:00
Ville Juven c1f3245167 riscv-v/fork.S: Fix clobbering of s0 in fork()
Value of s0 (callee-saved) must be preserved through the call, use
a0 (caller-saved) to calculate the original SP instead.
2024-05-31 02:29:48 +08:00
xuxin19 275ec7102c cmake:bugfix CMake compilation options settings should not use strings
when repeatedly enabling and disabling string-controlled configurations,
the generated toolchain configuration may be incorrect.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-05-30 10:02:10 -03:00
simbit18 fde641fac9 Fix Kconfig style
correct block name board
Remove extra TABs
Add comments
2024-05-29 17:15:57 -03:00
hujun5 c06c10f6f3 armv6/7/8-m: use ISB instruction immediately after the MSR instruction
when changing the stack pointer, software must use an
ISB instruction immediately after the MSR instruction.
This ensures that instructions after the ISB instruction
execute using the new stack pointer.

https://developer.arm.com/documentation/101928/0101/The-Cortex-M85-Processor--Reference-Material/Programmer-s-model/Core-registers/CONTROL-register?lang=en

" When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB instruction execute using the new stack pointer."

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-29 14:16:55 -03:00