boards/m100pfsevp: Decrease DDR lane temination values to 40 ohm and increase BCLKSCLK_OFFSET
This fixes problems with DDR training sequence on aries m100pfs board - Set LIBERO_SETTING_RPC_ODT_* to 6, which matches 40 ohm. Originally it was 120 ohm (2) - Set BCLKSCLK_OFFSET value to 5, which matches icicle board setting Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
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@ -76,10 +76,10 @@
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#define LIBERO_SETTING_DPC_BITS_OFF_MODE 0x00000000
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#define LIBERO_SETTING_DDRPHY_MODE 0x00002122
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#define LIBERO_SETTING_RPC_ODT_DQ 0x00000002
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#define LIBERO_SETTING_RPC_ODT_DQS 0x00000002
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#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000002
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#define LIBERO_SETTING_RPC_ODT_CLK 0x00000002
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#define LIBERO_SETTING_RPC_ODT_DQ 0x00000006
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#define LIBERO_SETTING_RPC_ODT_DQS 0x00000006
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#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000006
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#define LIBERO_SETTING_RPC_ODT_CLK 0x00000006
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#define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000000
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#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000003
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#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000dc4
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@ -575,7 +575,7 @@
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#define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2 3
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#define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_3 0
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#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE003
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#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02B
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#define LIBERO_SETTING_DDR_32_CACHE 0x80000000
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#define LIBERO_SETTING_DDR_32_CACHE_SIZE 0x100000
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