boards/m100pfsevp: Decrease DDR lane temination values to 40 ohm and increase BCLKSCLK_OFFSET

This fixes problems with DDR training sequence on aries m100pfs board

    - Set LIBERO_SETTING_RPC_ODT_* to 6, which matches 40 ohm. Originally it was 120 ohm (2)
    - Set BCLKSCLK_OFFSET value to 5, which matches icicle board setting

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit is contained in:
Jukka Laitinen 2021-12-29 15:49:17 +02:00 committed by Xiang Xiao
parent b92c90ee81
commit fc41bb7f8a
1 changed files with 5 additions and 5 deletions

View File

@ -76,10 +76,10 @@
#define LIBERO_SETTING_DPC_BITS_OFF_MODE 0x00000000
#define LIBERO_SETTING_DDRPHY_MODE 0x00002122
#define LIBERO_SETTING_RPC_ODT_DQ 0x00000002
#define LIBERO_SETTING_RPC_ODT_DQS 0x00000002
#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000002
#define LIBERO_SETTING_RPC_ODT_CLK 0x00000002
#define LIBERO_SETTING_RPC_ODT_DQ 0x00000006
#define LIBERO_SETTING_RPC_ODT_DQS 0x00000006
#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000006
#define LIBERO_SETTING_RPC_ODT_CLK 0x00000006
#define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000000
#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000003
#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000dc4
@ -575,7 +575,7 @@
#define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2 3
#define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_3 0
#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE003
#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02B
#define LIBERO_SETTING_DDR_32_CACHE 0x80000000
#define LIBERO_SETTING_DDR_32_CACHE_SIZE 0x100000