From fc41bb7f8ab8fbae2aad1cd191aefeab9e881903 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Wed, 29 Dec 2021 15:49:17 +0200 Subject: [PATCH] boards/m100pfsevp: Decrease DDR lane temination values to 40 ohm and increase BCLKSCLK_OFFSET This fixes problems with DDR training sequence on aries m100pfs board - Set LIBERO_SETTING_RPC_ODT_* to 6, which matches 40 ohm. Originally it was 120 ohm (2) - Set BCLKSCLK_OFFSET value to 5, which matches icicle board setting Signed-off-by: Jukka Laitinen --- .../risc-v/mpfs/m100pfsevp/include/board_liberodefs.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h b/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h index 798ffa8ae9..0d776674bb 100644 --- a/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h +++ b/boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h @@ -76,10 +76,10 @@ #define LIBERO_SETTING_DPC_BITS_OFF_MODE 0x00000000 #define LIBERO_SETTING_DDRPHY_MODE 0x00002122 -#define LIBERO_SETTING_RPC_ODT_DQ 0x00000002 -#define LIBERO_SETTING_RPC_ODT_DQS 0x00000002 -#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000002 -#define LIBERO_SETTING_RPC_ODT_CLK 0x00000002 +#define LIBERO_SETTING_RPC_ODT_DQ 0x00000006 +#define LIBERO_SETTING_RPC_ODT_DQS 0x00000006 +#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000006 +#define LIBERO_SETTING_RPC_ODT_CLK 0x00000006 #define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000000 #define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000003 #define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000dc4 @@ -575,7 +575,7 @@ #define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2 3 #define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_3 0 -#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE003 +#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02B #define LIBERO_SETTING_DDR_32_CACHE 0x80000000 #define LIBERO_SETTING_DDR_32_CACHE_SIZE 0x100000