Merge branch 'master' of bitbucket.org:nuttx/nuttx

arch/arm/src/stm32/stm32_rtcounter.c

@@ -379,12 +379,11 @@ int up_rtc_initialize(void)
 
   stm32_pwr_enablebkp(true);
   
-  /* Set access to the peripheral, enable the backup domain (BKP) and the lower
+  /* Select the lower power external 32,768Hz (Low-Speed External, LSE) oscillator
-   * power external 32,768Hz (Low-Speed External, LSE) oscillator.  Configure the
+   * as RTC Clock Source and enable the Clock */
-   * LSE to drive the RTC.
-   */
   
-  stm32_rcc_enablelse();
+  modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
+  modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
 
   /* TODO: Get state from this function, if everything is
    *   okay and whether it is already enabled (if it was disabled

arch/arm/src/stm32/stm32f10xxx_rcc.c

@@ -756,12 +756,6 @@ static void stm32_stdclockconfig(void)
 
   stm32_rcc_enablelsi();
 #endif
-
-#if defined(CONFIG_RTC_LSECLOCK)
-  /* Low speed external clock source LSE */
-
-  stm32_rcc_enablelse();
-#endif
 }
 #endif
 
@@ -774,6 +768,14 @@ static inline void rcc_enableperipherals(void)
   rcc_enableahb();
   rcc_enableapb2();
   rcc_enableapb1();
+
+#if defined(CONFIG_RTC_LSECLOCK)
+  /* Low speed external clock source LSE
+   * For F1 it requires PWR and BKP from APB1
+   */
+
+  stm32_rcc_enablelse();
+#endif
 }
 
 /****************************************************************************