From 0d0b1b64e2f4a3a48a47024b23160fa3b120651d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20W=C3=B3jcik?= Date: Fri, 25 Nov 2016 06:17:18 +0100 Subject: [PATCH] Fix for F1 RTC Clock, tested on F103 --- arch/arm/src/stm32/stm32_rtcounter.c | 13 ++++++------- arch/arm/src/stm32/stm32f10xxx_rcc.c | 14 ++++++++------ 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/stm32/stm32_rtcounter.c index 137e7344a0..1c90be9c14 100644 --- a/arch/arm/src/stm32/stm32_rtcounter.c +++ b/arch/arm/src/stm32/stm32_rtcounter.c @@ -378,13 +378,12 @@ int up_rtc_initialize(void) */ stm32_pwr_enablebkp(true); - - /* Set access to the peripheral, enable the backup domain (BKP) and the lower - * power external 32,768Hz (Low-Speed External, LSE) oscillator. Configure the - * LSE to drive the RTC. - */ - - stm32_rcc_enablelse(); + + /* Select the lower power external 32,768Hz (Low-Speed External, LSE) oscillator + * as RTC Clock Source and enable the Clock */ + + modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); /* TODO: Get state from this function, if everything is * okay and whether it is already enabled (if it was disabled diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32/stm32f10xxx_rcc.c index 736b3ee7ef..218e534e22 100644 --- a/arch/arm/src/stm32/stm32f10xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f10xxx_rcc.c @@ -756,12 +756,6 @@ static void stm32_stdclockconfig(void) stm32_rcc_enablelsi(); #endif - -#if defined(CONFIG_RTC_LSECLOCK) - /* Low speed external clock source LSE */ - - stm32_rcc_enablelse(); -#endif } #endif @@ -774,6 +768,14 @@ static inline void rcc_enableperipherals(void) rcc_enableahb(); rcc_enableapb2(); rcc_enableapb1(); + +#if defined(CONFIG_RTC_LSECLOCK) + /* Low speed external clock source LSE + * For F1 it requires PWR and BKP from APB1 + */ + + stm32_rcc_enablelse(); +#endif } /****************************************************************************