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Beginning of support for SAMA5 EHCI. Not much there yet

This commit is contained in:
Gregory Nutt 2013-08-20 15:46:36 -06:00
parent 1d56a5c9fd
commit bc57cd5684
2 changed files with 35 additions and 3 deletions
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2
configs/sama5d3x-ek/include/board_384mhz.h
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@ -100,6 +100,7 @@
#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2 #define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2
#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3 #define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3
#ifdef CONFIG_SAMA5_OHCI
/* For OHCI Full-speed operations, the user has to perform the following: /* For OHCI Full-speed operations, the user has to perform the following:
* *
* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER
@ -133,6 +134,7 @@
# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA # define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA
# define BOARD_OHCI_DIVIDER (7) # define BOARD_OHCI_DIVIDER (7)
#endif
/* Resulting frequencies */ /* Resulting frequencies */

32
configs/sama5d3x-ek/include/board_396mhz.h
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@ -98,7 +98,7 @@
#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1 #define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2 #define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2
#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3 #define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3
786
/* Resulting frequencies */ /* Resulting frequencies */
#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */ #define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
@ -106,6 +106,36 @@
#define BOARD_PCK_FREQUENCY (396000000) /* CPU: PLLACK / 2 / 1 */ #define BOARD_PCK_FREQUENCY (396000000) /* CPU: PLLACK / 2 / 1 */
#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */ #define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */
#ifdef CONFIG_SAMA5_EHCI
/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
* High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
* (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
* the 12MHz internal RC oscillator on a an external 12MHz crystal. The
* Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier.
*
* For High-speed operations, the user has to perform the following:
*
* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
* PMC_PCER register.
* 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
* 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
* 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
* 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
* 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
* register.
* 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
* selected.
* 8) Enable OHCI clocks, UHP bit in PMC_SCER register.
*
* Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI
* driver is initialized.
*/
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
#endif
/* HSMCI clocking /* HSMCI clocking
* *
* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)