From bc57cd5684005e70620776f9d51852bb41e1eaca Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 20 Aug 2013 15:46:36 -0600 Subject: [PATCH] Beginning of support for SAMA5 EHCI. Not much there yet --- configs/sama5d3x-ek/include/board_384mhz.h | 6 ++-- configs/sama5d3x-ek/include/board_396mhz.h | 32 +++++++++++++++++++++- 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/configs/sama5d3x-ek/include/board_384mhz.h b/configs/sama5d3x-ek/include/board_384mhz.h index 74494cbb25..8f94da2edf 100644 --- a/configs/sama5d3x-ek/include/board_384mhz.h +++ b/configs/sama5d3x-ek/include/board_384mhz.h @@ -100,6 +100,7 @@ #define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2 #define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3 +#ifdef CONFIG_SAMA5_OHCI /* For OHCI Full-speed operations, the user has to perform the following: * * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER @@ -131,8 +132,9 @@ * frame rate. I cannot explain the factor of 2 difference. */ -#define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA -#define BOARD_OHCI_DIVIDER (7) +# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA +# define BOARD_OHCI_DIVIDER (7) +#endif /* Resulting frequencies */ diff --git a/configs/sama5d3x-ek/include/board_396mhz.h b/configs/sama5d3x-ek/include/board_396mhz.h index f98cbac863..ac3ae724ec 100644 --- a/configs/sama5d3x-ek/include/board_396mhz.h +++ b/configs/sama5d3x-ek/include/board_396mhz.h @@ -98,7 +98,7 @@ #define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1 #define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2 #define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3 -786 + /* Resulting frequencies */ #define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */ @@ -106,6 +106,36 @@ #define BOARD_PCK_FREQUENCY (396000000) /* CPU: PLLACK / 2 / 1 */ #define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */ +#ifdef CONFIG_SAMA5_EHCI +/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded + * High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL + * (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either + * the 12MHz internal RC oscillator on a an external 12MHz crystal. The + * Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier. + * + * For High-speed operations, the user has to perform the following: + * + * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in + * PMC_PCER register. + * 2) Write CKGR_PLLCOUNT field in PMC_UCKR register. + * 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register. + * 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register + * 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register. + * 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB + * register. + * 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in + * PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is + * selected. + * 8) Enable OHCI clocks, UHP bit in PMC_SCER register. + * + * Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI + * driver is initialized. + */ + +# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ +# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ +#endif + /* HSMCI clocking * * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)