SAMA5: Add support for Micrel KSZ8081 PHY
This commit is contained in:
Gregory Nutt
parent
8b450d6d1b
commit
69c18728f2
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@ -161,6 +161,9 @@
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#elif defined(SAMA5_EMAC_PHY_KSZ8051)
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# define MII_OUI_MSB 0x0022
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# define MII_OUI_LSB 0x05
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#elif defined(SAMA5_EMAC_PHY_KSZ8081)
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# define MII_OUI_MSB 0x0022
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# define MII_OUI_LSB 0x05
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#else
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# error EMAC PHY unrecognized
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#endif
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@ -158,14 +158,17 @@
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/* PHY definitions */
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#if defined(SAMA5_EMAC0_PHY_DM9161)
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# define MII_OUI_MSB 0x0181
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# define MII_OUI_LSB 0x2e
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# define EMAC0_MII_OUI_MSB 0x0181
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# define EMAC0_MII_OUI_LSB 0x2e
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#elif defined(SAMA5_EMAC0_PHY_LAN8700)
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# define MII_OUI_MSB 0x0007
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# define MII_OUI_LSB 0x30
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# define EMAC0_MII_OUI_MSB 0x0007
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# define EMAC0_MII_OUI_LSB 0x30
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#elif defined(SAMA5_EMAC0_PHY_KSZ8051)
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# define MII_OUI_MSB 0x0022
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# define MII_OUI_LSB 0x05
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# define EMAC0_MII_OUI_MSB 0x0022
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# define EMAC0_MII_OUI_LSB 0x05
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#elif defined(SAMA5_EMAC_PHY_KSZ8081)
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# define EMAC0_MII_OUI_MSB 0x0022
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# define EMAC0_MII_OUI_LSB 0x05
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#else
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# error EMAC PHY unrecognized
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#endif
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@ -235,14 +238,17 @@
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/* PHY definitions */
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#if defined(SAMA5_EMAC1_PHY_DM9161)
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# define MII_OUI_MSB 0x0181
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# define MII_OUI_LSB 0x2e
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# define EMAC1_MII_OUI_MSB 0x0181
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# define EMAC1_MII_OUI_LSB 0x2e
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#elif defined(SAMA5_EMAC1_PHY_LAN8700)
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# define MII_OUI_MSB 0x0007
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# define MII_OUI_LSB 0x30
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# define EMAC1_MII_OUI_MSB 0x0007
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# define EMAC1_MII_OUI_LSB 0x30
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#elif defined(SAMA5_EMAC1_PHY_KSZ8051)
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# define MII_OUI_MSB 0x0022
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# define MII_OUI_LSB 0x05
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# define EMAC1_MII_OUI_MSB 0x0022
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# define EMAC1_MII_OUI_LSB 0x05
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#elif defined(SAMA5_EMAC1_PHY_KSZ8081)
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# define EMAC1_MII_OUI_MSB 0x0022
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# define EMAC1_MII_OUI_LSB 0x05
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#else
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# error EMAC PHY unrecognized
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#endif
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@ -322,6 +328,8 @@ struct sam_emacattr_s
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uint8_t phyaddr; /* PHY address */
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uint8_t physr; /* PHY status register address */
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uint16_t msoui; /* MS 16 bits of the 18-bit OUI */
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uint8_t lsoui; /* LS 2 bits of the 18-bit OUI */
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bool rmii; /* True: RMII vs. False: MII */
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bool clause45; /* True: Clause 45 behavior */
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//bool autoneg; /* True: Autonegotiate rate and *plex */
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@ -577,6 +585,8 @@ static const struct sam_emacattr_s g_emac0_attr =
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.phyaddr = CONFIG_SAMA5_EMAC0_PHYADDR,
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.physr = CONFIG_SAMA5_EMAC0_PHYSR,
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.msoui = EMAC0_MII_OUI_MSB,
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.lsoui = EMAC0_MII_OUI_LSB,
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#ifdef CONFIG_SAMA5_EMAC0_RMII
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.rmii = true,
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#endif
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@ -643,6 +653,8 @@ static const struct sam_emacattr_s g_emac1_attr =
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.phyaddr = CONFIG_SAMA5_EMAC1_PHYADDR,
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.physr = CONFIG_SAMA5_EMAC1_PHYSR,
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.msoui = EMAC1_MII_OUI_MSB,
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.lsoui = EMAC1_MII_OUI_LSB,
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#ifdef CONFIG_SAMA5_EMAC1_RMII
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.rmii = true,
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#endif
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@ -2400,7 +2412,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
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/* Check current candidate address */
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ret = sam_phyread(priv, candidate, MII_PHYID1, &phyval);
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if (ret == OK && phyval == MII_OUI_MSB)
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if (ret == OK && phyval == priv->attr->msoui)
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{
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*phyaddr = candidate;
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ret = OK;
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@ -2422,7 +2434,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr)
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/* Try reading the PHY ID from the candidate PHY address */
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ret = sam_phyread(priv, candidate, MII_PHYID1, &phyval);
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if (ret == OK && phyval == MII_OUI_MSB)
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if (ret == OK && phyval == priv->attr->msoui)
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{
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ret = OK;
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break;
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@ -2625,8 +2637,9 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
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nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
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if (phyid1 == MII_OUI_MSB &&
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((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
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if (phyid1 == priv->attr->msoui &&
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((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) ==
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(uint16_t)priv->attr->lsoui)
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{
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nllvdbg(" Vendor Model Number: %04x\n",
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(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
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@ -115,6 +115,8 @@
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# define SAMA5_EMAC_PHY_LAN8700 1
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# elif defined(CONFIG_ETH0_PHY_KSZ8051)
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# define SAMA5_EMAC_PHY_KSZ8051 1
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# elif defined(CONFIG_ETH0_PHY_KSZ8081)
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# define SAMA5_EMAC_PHY_KSZ8081 1
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# elif defined(CONFIG_ETH0_PHY_KSZ90x1)
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# define SAMA5_EMAC_PHY_KSZ90x1 1
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# else
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@ -127,6 +129,8 @@
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# define SAMA5_EMAC_PHY_LAN8700 1
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# elif defined(CONFIG_ETH1_PHY_KSZ8051)
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# define SAMA5_EMAC_PHY_KSZ8051 1
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# elif defined(CONFIG_ETH1_PHY_KSZ8081)
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# define SAMA5_EMAC_PHY_KSZ8081 1
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# elif defined(CONFIG_ETH1_PHY_KSZ90x1)
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# define SAMA5_EMAC_PHY_KSZ90x1 1
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# else
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@ -141,6 +145,8 @@
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# define SAMA5_EMAC0_PHY_LAN8700 1
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# elif defined(CONFIG_ETH0_PHY_KSZ8051)
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# define SAMA5_EMAC0_PHY_KSZ8051 1
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# elif defined(CONFIG_ETH0_PHY_KSZ8081)
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# define SAMA5_EMAC0_PHY_KSZ8081 1
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# elif defined(CONFIG_ETH0_PHY_KSZ90x1)
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# define SAMA5_EMAC0_PHY_KSZ90x1 1
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# else
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@ -153,6 +159,8 @@
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# define SAMA5_EMAC0_PHY_LAN8700 1
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# elif defined(CONFIG_ETH1_PHY_KSZ8051)
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# define SAMA5_EMAC0_PHY_KSZ8051 1
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# elif defined(CONFIG_ETH0_PHY_KSZ8081)
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# define SAMA5_EMAC0_PHY_KSZ8081 1
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# elif defined(CONFIG_ETH1_PHY_KSZ90x1)
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# define SAMA5_EMAC0_PHY_KSZ90x1 1
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# else
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@ -167,6 +175,8 @@
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# define SAMA5_EMAC1_PHY_LAN8700 1
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# elif defined(CONFIG_ETH0_PHY_KSZ8051)
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# define SAMA5_EMAC1_PHY_KSZ8051 1
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# elif defined(CONFIG_ETH0_PHY_KSZ8081)
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# define SAMA5_EMAC1_PHY_KSZ8081 1
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# elif defined(CONFIG_ETH0_PHY_KSZ90x1)
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# define SAMA5_EMAC1_PHY_KSZ90x1 1
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# else
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@ -179,6 +189,8 @@
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# define SAMA5_EMAC1_PHY_LAN8700 1
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# elif defined(CONFIG_ETH1_PHY_KSZ8051)
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# define SAMA5_EMAC1_PHY_KSZ8051 1
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# elif defined(CONFIG_ETH0_PHY_KSZ8081)
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# define SAMA5_EMAC1_PHY_KSZ8081 1
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# elif defined(CONFIG_ETH1_PHY_KSZ90x1)
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# define SAMA5_EMAC1_PHY_KSZ90x1 1
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# else
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@ -1,7 +1,7 @@
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/****************************************************************************
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* include/nuttx/net/mii.h
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*
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* Copyright (C) 2008-2010, 2012-2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2008-2010, 2012-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -110,9 +110,9 @@
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#define MII_KS8721_INTCS 0x1b /* Interrupt control/status register */
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#define MII_KS8721_10BTCR 0x1f /* 10BASE-TX PHY control register */
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/* Micrel KSZ805: 0x11, 0x15-0x18, 0x1b, 0x1d, 0x1e-0x1f */
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/* Micrel KSZ8051: 0x11, 0x15-0x18, 0x1b, 0x1d-0x1f */
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#define MII_KSZ8051_AFEC1 0x11 /* AFE Control 1 */
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#define MII_KSZ8051_AFEC1 0x11 /* AFE Control 1 */
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#define MII_KSZ8051_RXERR 0x15 /* RXERR Counter */
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#define MII_KSZ8051_OMSO 0x16 /* Operation Mode Strap Override */
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#define MII_KSZ8051_OMSS 0x17 /* Operation Mode Strap Status */
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@ -122,6 +122,19 @@
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#define MII_KSZ8051_PHYCTRL1 0x1e /* PHY Control 1 */
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#define MII_KSZ8051_PHYCTRL2 0x1f /* PHY Control 2 */
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/* Micrel KSZ8081: 0x10-0x11, 0x15-0x18, 0x1b, 0x1d-0x1f */
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#define MII_KSZ8081_DRCTRL 0x10 /* Digital Reserve Control */
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#define MII_KSZ8081_AFEC1 0x11 /* AFE Control 1 */
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#define MII_KSZ8081_RXERR 0x15 /* RXERR Counter */
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#define MII_KSZ8081_OMSO 0x16 /* Operation Mode Strap Override */
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#define MII_KSZ8081_OMSS 0x17 /* Operation Mode Strap Status */
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#define MII_KSZ8081_XCTRL 0x18 /* Expanded Control */
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#define MII_KSZ8081_INT 0x1b /* Interrupt Control/Status */
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#define MII_KSZ8081_LINKMD 0x1d /* LinkMD(c) Control/Status */
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#define MII_KSZ8081_PHYCTRL1 0x1e /* PHY Control 1 */
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#define MII_KSZ8081_PHYCTRL2 0x1f /* PHY Control 2 */
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/* National Semiconductor DP83848C PHY Extended Registers. 0x8-0x15, 0x13, 0x1c reserved */
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#define MII_DP83848C_STS 0x10 /* RO PHY Status Register */
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@ -461,13 +474,20 @@
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#define KS8721_10BTCR_ENERGY (1 << 12) /* Bit 12: Energy detect */
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#define KS8721_10BTCR_PAIRSWAPD (1 << 13) /* Bit 13: Pairswap disable */
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/* KSZ8051-specific register bit settings ***********************************/
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/* KSZ805 MII ID1/2 register bits */
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/* KSZ8051/81-specific register bit settings ********************************/
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/* KSZ8051/81 MII ID1/2 register bits */
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#define MII_PHYID1_KSZ8051 0x0022 /* ID1 value for Micrel KSZ8051 */
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#define MII_PHYID2_KSZ8051 0x1550 /* ID2 value for Micrel KSZ8051 */
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/* KSZ805 Register 0x1e: PHY Control 1 */
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#define MII_PHYID1_KSZ8081 0x0022 /* ID1 value for Micrel KSZ8081 */
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#define MII_PHYID2_KSZ8081 0x1560 /* ID2 value for Micrel KSZ8081 */
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/* KSZ8081 Digital Reserve Control */
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/* Bits 5-15: Reserved */
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#define KSZ8081_DRCTRL_PLLOFF (1 << 4) /* Bit 4: Turn PLL off in EDPD mode */
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/* Bits 0-3: Reserved */
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/* KSZ8051/81 Register 0x1e: PHY Control 1 */
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/* Bits 10-15: Reserved */
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#define MII_PHYCTRL1_ENPAUSE (1 << 9) /* Bit 9: Enable pause */
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#define MII_PHYCTRL1_LINKSTATUS (1 << 8) /* Bit 8: Link status */
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