diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index 6107e04e63..f2cc702df2 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -161,6 +161,9 @@ #elif defined(SAMA5_EMAC_PHY_KSZ8051) # define MII_OUI_MSB 0x0022 # define MII_OUI_LSB 0x05 +#elif defined(SAMA5_EMAC_PHY_KSZ8081) +# define MII_OUI_MSB 0x0022 +# define MII_OUI_LSB 0x05 #else # error EMAC PHY unrecognized #endif diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index 88af28d61b..d0c756fba9 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -158,14 +158,17 @@ /* PHY definitions */ #if defined(SAMA5_EMAC0_PHY_DM9161) -# define MII_OUI_MSB 0x0181 -# define MII_OUI_LSB 0x2e +# define EMAC0_MII_OUI_MSB 0x0181 +# define EMAC0_MII_OUI_LSB 0x2e #elif defined(SAMA5_EMAC0_PHY_LAN8700) -# define MII_OUI_MSB 0x0007 -# define MII_OUI_LSB 0x30 +# define EMAC0_MII_OUI_MSB 0x0007 +# define EMAC0_MII_OUI_LSB 0x30 #elif defined(SAMA5_EMAC0_PHY_KSZ8051) -# define MII_OUI_MSB 0x0022 -# define MII_OUI_LSB 0x05 +# define EMAC0_MII_OUI_MSB 0x0022 +# define EMAC0_MII_OUI_LSB 0x05 +#elif defined(SAMA5_EMAC_PHY_KSZ8081) +# define EMAC0_MII_OUI_MSB 0x0022 +# define EMAC0_MII_OUI_LSB 0x05 #else # error EMAC PHY unrecognized #endif @@ -235,14 +238,17 @@ /* PHY definitions */ #if defined(SAMA5_EMAC1_PHY_DM9161) -# define MII_OUI_MSB 0x0181 -# define MII_OUI_LSB 0x2e +# define EMAC1_MII_OUI_MSB 0x0181 +# define EMAC1_MII_OUI_LSB 0x2e #elif defined(SAMA5_EMAC1_PHY_LAN8700) -# define MII_OUI_MSB 0x0007 -# define MII_OUI_LSB 0x30 +# define EMAC1_MII_OUI_MSB 0x0007 +# define EMAC1_MII_OUI_LSB 0x30 #elif defined(SAMA5_EMAC1_PHY_KSZ8051) -# define MII_OUI_MSB 0x0022 -# define MII_OUI_LSB 0x05 +# define EMAC1_MII_OUI_MSB 0x0022 +# define EMAC1_MII_OUI_LSB 0x05 +#elif defined(SAMA5_EMAC1_PHY_KSZ8081) +# define EMAC1_MII_OUI_MSB 0x0022 +# define EMAC1_MII_OUI_LSB 0x05 #else # error EMAC PHY unrecognized #endif @@ -322,6 +328,8 @@ struct sam_emacattr_s uint8_t phyaddr; /* PHY address */ uint8_t physr; /* PHY status register address */ + uint16_t msoui; /* MS 16 bits of the 18-bit OUI */ + uint8_t lsoui; /* LS 2 bits of the 18-bit OUI */ bool rmii; /* True: RMII vs. False: MII */ bool clause45; /* True: Clause 45 behavior */ //bool autoneg; /* True: Autonegotiate rate and *plex */ @@ -577,6 +585,8 @@ static const struct sam_emacattr_s g_emac0_attr = .phyaddr = CONFIG_SAMA5_EMAC0_PHYADDR, .physr = CONFIG_SAMA5_EMAC0_PHYSR, + .msoui = EMAC0_MII_OUI_MSB, + .lsoui = EMAC0_MII_OUI_LSB, #ifdef CONFIG_SAMA5_EMAC0_RMII .rmii = true, #endif @@ -643,6 +653,8 @@ static const struct sam_emacattr_s g_emac1_attr = .phyaddr = CONFIG_SAMA5_EMAC1_PHYADDR, .physr = CONFIG_SAMA5_EMAC1_PHYSR, + .msoui = EMAC1_MII_OUI_MSB, + .lsoui = EMAC1_MII_OUI_LSB, #ifdef CONFIG_SAMA5_EMAC1_RMII .rmii = true, #endif @@ -2400,7 +2412,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr) /* Check current candidate address */ ret = sam_phyread(priv, candidate, MII_PHYID1, &phyval); - if (ret == OK && phyval == MII_OUI_MSB) + if (ret == OK && phyval == priv->attr->msoui) { *phyaddr = candidate; ret = OK; @@ -2422,7 +2434,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr) /* Try reading the PHY ID from the candidate PHY address */ ret = sam_phyread(priv, candidate, MII_PHYID1, &phyval); - if (ret == OK && phyval == MII_OUI_MSB) + if (ret == OK && phyval == priv->attr->msoui) { ret = OK; break; @@ -2625,8 +2637,9 @@ static int sam_autonegotiate(struct sam_emac_s *priv) nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr); - if (phyid1 == MII_OUI_MSB && - ((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB) + if (phyid1 == priv->attr->msoui && + ((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == + (uint16_t)priv->attr->lsoui) { nllvdbg(" Vendor Model Number: %04x\n", (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT); diff --git a/arch/arm/src/sama5/sam_ethernet.h b/arch/arm/src/sama5/sam_ethernet.h index 9733ebb70f..c2a88349f7 100644 --- a/arch/arm/src/sama5/sam_ethernet.h +++ b/arch/arm/src/sama5/sam_ethernet.h @@ -115,6 +115,8 @@ # define SAMA5_EMAC_PHY_LAN8700 1 # elif defined(CONFIG_ETH0_PHY_KSZ8051) # define SAMA5_EMAC_PHY_KSZ8051 1 +# elif defined(CONFIG_ETH0_PHY_KSZ8081) +# define SAMA5_EMAC_PHY_KSZ8081 1 # elif defined(CONFIG_ETH0_PHY_KSZ90x1) # define SAMA5_EMAC_PHY_KSZ90x1 1 # else @@ -127,6 +129,8 @@ # define SAMA5_EMAC_PHY_LAN8700 1 # elif defined(CONFIG_ETH1_PHY_KSZ8051) # define SAMA5_EMAC_PHY_KSZ8051 1 +# elif defined(CONFIG_ETH1_PHY_KSZ8081) +# define SAMA5_EMAC_PHY_KSZ8081 1 # elif defined(CONFIG_ETH1_PHY_KSZ90x1) # define SAMA5_EMAC_PHY_KSZ90x1 1 # else @@ -141,6 +145,8 @@ # define SAMA5_EMAC0_PHY_LAN8700 1 # elif defined(CONFIG_ETH0_PHY_KSZ8051) # define SAMA5_EMAC0_PHY_KSZ8051 1 +# elif defined(CONFIG_ETH0_PHY_KSZ8081) +# define SAMA5_EMAC0_PHY_KSZ8081 1 # elif defined(CONFIG_ETH0_PHY_KSZ90x1) # define SAMA5_EMAC0_PHY_KSZ90x1 1 # else @@ -153,6 +159,8 @@ # define SAMA5_EMAC0_PHY_LAN8700 1 # elif defined(CONFIG_ETH1_PHY_KSZ8051) # define SAMA5_EMAC0_PHY_KSZ8051 1 +# elif defined(CONFIG_ETH0_PHY_KSZ8081) +# define SAMA5_EMAC0_PHY_KSZ8081 1 # elif defined(CONFIG_ETH1_PHY_KSZ90x1) # define SAMA5_EMAC0_PHY_KSZ90x1 1 # else @@ -167,6 +175,8 @@ # define SAMA5_EMAC1_PHY_LAN8700 1 # elif defined(CONFIG_ETH0_PHY_KSZ8051) # define SAMA5_EMAC1_PHY_KSZ8051 1 +# elif defined(CONFIG_ETH0_PHY_KSZ8081) +# define SAMA5_EMAC1_PHY_KSZ8081 1 # elif defined(CONFIG_ETH0_PHY_KSZ90x1) # define SAMA5_EMAC1_PHY_KSZ90x1 1 # else @@ -179,6 +189,8 @@ # define SAMA5_EMAC1_PHY_LAN8700 1 # elif defined(CONFIG_ETH1_PHY_KSZ8051) # define SAMA5_EMAC1_PHY_KSZ8051 1 +# elif defined(CONFIG_ETH0_PHY_KSZ8081) +# define SAMA5_EMAC1_PHY_KSZ8081 1 # elif defined(CONFIG_ETH1_PHY_KSZ90x1) # define SAMA5_EMAC1_PHY_KSZ90x1 1 # else diff --git a/include/nuttx/net/mii.h b/include/nuttx/net/mii.h index 749bdb2cc8..47726c14e4 100644 --- a/include/nuttx/net/mii.h +++ b/include/nuttx/net/mii.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/nuttx/net/mii.h * - * Copyright (C) 2008-2010, 2012-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2010, 2012-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -110,9 +110,9 @@ #define MII_KS8721_INTCS 0x1b /* Interrupt control/status register */ #define MII_KS8721_10BTCR 0x1f /* 10BASE-TX PHY control register */ -/* Micrel KSZ805: 0x11, 0x15-0x18, 0x1b, 0x1d, 0x1e-0x1f */ +/* Micrel KSZ8051: 0x11, 0x15-0x18, 0x1b, 0x1d-0x1f */ -#define MII_KSZ8051_AFEC1 0x11 /* AFE Control 1 */ +#define MII_KSZ8051_AFEC1 0x11 /* AFE Control 1 */ #define MII_KSZ8051_RXERR 0x15 /* RXERR Counter */ #define MII_KSZ8051_OMSO 0x16 /* Operation Mode Strap Override */ #define MII_KSZ8051_OMSS 0x17 /* Operation Mode Strap Status */ @@ -122,6 +122,19 @@ #define MII_KSZ8051_PHYCTRL1 0x1e /* PHY Control 1 */ #define MII_KSZ8051_PHYCTRL2 0x1f /* PHY Control 2 */ +/* Micrel KSZ8081: 0x10-0x11, 0x15-0x18, 0x1b, 0x1d-0x1f */ + +#define MII_KSZ8081_DRCTRL 0x10 /* Digital Reserve Control */ +#define MII_KSZ8081_AFEC1 0x11 /* AFE Control 1 */ +#define MII_KSZ8081_RXERR 0x15 /* RXERR Counter */ +#define MII_KSZ8081_OMSO 0x16 /* Operation Mode Strap Override */ +#define MII_KSZ8081_OMSS 0x17 /* Operation Mode Strap Status */ +#define MII_KSZ8081_XCTRL 0x18 /* Expanded Control */ +#define MII_KSZ8081_INT 0x1b /* Interrupt Control/Status */ +#define MII_KSZ8081_LINKMD 0x1d /* LinkMD(c) Control/Status */ +#define MII_KSZ8081_PHYCTRL1 0x1e /* PHY Control 1 */ +#define MII_KSZ8081_PHYCTRL2 0x1f /* PHY Control 2 */ + /* National Semiconductor DP83848C PHY Extended Registers. 0x8-0x15, 0x13, 0x1c reserved */ #define MII_DP83848C_STS 0x10 /* RO PHY Status Register */ @@ -461,13 +474,20 @@ #define KS8721_10BTCR_ENERGY (1 << 12) /* Bit 12: Energy detect */ #define KS8721_10BTCR_PAIRSWAPD (1 << 13) /* Bit 13: Pairswap disable */ -/* KSZ8051-specific register bit settings ***********************************/ -/* KSZ805 MII ID1/2 register bits */ +/* KSZ8051/81-specific register bit settings ********************************/ +/* KSZ8051/81 MII ID1/2 register bits */ #define MII_PHYID1_KSZ8051 0x0022 /* ID1 value for Micrel KSZ8051 */ #define MII_PHYID2_KSZ8051 0x1550 /* ID2 value for Micrel KSZ8051 */ -/* KSZ805 Register 0x1e: PHY Control 1 */ +#define MII_PHYID1_KSZ8081 0x0022 /* ID1 value for Micrel KSZ8081 */ +#define MII_PHYID2_KSZ8081 0x1560 /* ID2 value for Micrel KSZ8081 */ + +/* KSZ8081 Digital Reserve Control */ + /* Bits 5-15: Reserved */ +#define KSZ8081_DRCTRL_PLLOFF (1 << 4) /* Bit 4: Turn PLL off in EDPD mode */ + /* Bits 0-3: Reserved */ +/* KSZ8051/81 Register 0x1e: PHY Control 1 */ /* Bits 10-15: Reserved */ #define MII_PHYCTRL1_ENPAUSE (1 << 9) /* Bit 9: Enable pause */ #define MII_PHYCTRL1_LINKSTATUS (1 << 8) /* Bit 8: Link status */