Run arch files through nxstyle.
This commit is contained in:
Gregory Nutt
Abdelatif Guettouche
parent
77b4fa936b
commit
647f2f44df
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@ -49,11 +49,11 @@
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* Pre-processor Definitions
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************************************************************************************/
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/* SPIC Registers *****************************************************************/
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/* SPIC Registers ******************************************************************/
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/* Provided in ez80f91.h */
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/* SPIC Register Bit Definitions **************************************************/
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/* SPIC Register Bit Definitions ***************************************************/
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/* Baud Rate Generator (BRG) H/L Register Definitions
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*
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@ -97,7 +97,7 @@ extern "C"
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#endif /* __cplusplus */
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/************************************************************************************
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* Public Functions
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* Public Function Prototypes
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************************************************************************************/
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/************************************************************************************
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@ -16,22 +16,22 @@
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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*********************************************************************************;
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#ifndef __ARCH_Z80_SRC_EZ80_EZ80F92_H
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#define __ARCH_Z80_SRC_EZ80_EZ80F92_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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*********************************************************************************;
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#include "ez80f91_emac.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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*********************************************************************************;
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/* Memory map ***********************************************************************/
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/* Memory map ********************************************************************;
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#define EZ80_ONCHIPFLASH 0x000000 /* CS0: 128Kb of on-chip flash */
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#define EZ80_OFFCHIPCS0 0x400000 /* CS0: Off chip use (usually flash) */
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@ -39,13 +39,13 @@
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#define EZ80_OFFCHIPCS1 0xc00000 /* CS1: Off chip use (usually SRAM) */
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#define EZ80_ONCHIPSRAM 0xffe000 /* On-chip SRAM (8Kb) on reset */
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/* Product ID Registers ************************************************************/
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/* Product ID Registers *********************************************************;
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#define EZ80_ZDI_ID_L 0x00
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#define EZ80_ZDI_ID_H 0x01
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#define EZ80_ZDI_ID_REV 0x02
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/* Timer Registers *****************************************************************/
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/* Timer Registers **************************************************************;
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#define EZ80_TMR0_CTL 0x80 /* RW: Timer 0 control register */
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#define EZ80_TMR0_DRL 0x81 /* R : Timer 0 data register (low) */
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@ -85,7 +85,7 @@
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#define EZ80_TMR_ISS 0x92 /* Timer input source selection register */
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/* TMR0/1/2/3 CTL Register Bit Definitions *******************************************/
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/* TMR0/1/2/3 CTL Register Bit Definitions ******************************************/
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#define EZ80_TMRCTL_IRQ 0x80 /* Bit 7: Generate interrupt request */
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#define EZ80_TMRCTL_EN 0x40 /* Bit 6: Enable timer interrupt requests */
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@ -99,12 +99,12 @@
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#define EZ80_TMRCTL_RSTEN 0x02 /* Bit 1: Reload and start function enabled */
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#define EZ80_TMRCTL_TIMEN 0x01 /* Bit 0: Programmable reload timer enabled */
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/* WDT Registers *********************************************************************/
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/* WDT Registers ********************************************************************/
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#define EZ80_WDT_CTL 0x93
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#define EZ80_WDT_RR 0x94
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/* GPIO Registers ********************************************************************/
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/* GPIO Registers *******************************************************************/
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#define EZ80_PB_DR 0x9a
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#define EZ80_PB_DDR 0x9b
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@ -119,7 +119,7 @@
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#define EZ80_PD_ALT1 0xa4
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#define EZ80_PD_ALT2 0xa5
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/* CS Registers **********************************************************************/
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/* CS Registers *********************************************************************/
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#define EZ80_CS0_LBR 0xa8
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#define EZ80_CS0_UBR 0xa9
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@ -134,17 +134,17 @@
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#define EZ80_CS3_UBR 0xb2
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#define EZ80_CS3_CTL 0xb3
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/* RAMCTL registers ******************************************************************/
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/* RAMCTL registers *****************************************************************/
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#define EZ80_RAM_CTL 0xb4
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#define EZ80_RAM_ADDR_U 0xb5
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/* RAMCTL bit definitions ************************************************************/
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/* RAMCTL bit definitions ***********************************************************/
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#define RAMCTL_ERAMEN (1 << 6) /* Bit 7: 1=On chip EMAC SRAM is enabled */
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#define RAMCTL_GPRAMEN (1 << 7) /* Bit 7: 1=On chip GP SRAM is enabled */
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/* SPI Registers *********************************************************************/
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/* SPI Registers ********************************************************************/
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#define EZ80_SPI_BRG_L 0xb8
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#define EZ80_SPI_BRG_H 0xb9
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@ -153,11 +153,11 @@
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#define EZ80_SPI_RBR 0xbc
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#define EZ80_SPI_TSR 0xbc
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/* Infrared Encoder/Decoder Block ****************************************************/
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/* Infrared Encoder/Decoder Block ***************************************************/
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#define EZ80_IR_CTL 0xbf /* Infrared Encoder/Decoder Control */
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/* UART Register Offsets *************************************************************/
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/* UART Register Offsets ************************************************************/
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/* DLAB=0: */
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#define EZ80_UART_THR 0x00 /* W: UART Transmit holding register */
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#define EZ80_UART_RBR 0x00 /* R : UART Receive buffer register */
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