From 647f2f44df2f54567843e049222f3ec22d396303 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Feb 2020 16:29:33 -0600 Subject: [PATCH] Run arch files through nxstyle. --- arch/z80/src/ez80/ez80f91_spi.h | 6 +++--- arch/z80/src/ez80/ez80f92.h | 30 +++++++++++++++--------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/z80/src/ez80/ez80f91_spi.h b/arch/z80/src/ez80/ez80f91_spi.h index c1f9b635db..97911d1822 100644 --- a/arch/z80/src/ez80/ez80f91_spi.h +++ b/arch/z80/src/ez80/ez80f91_spi.h @@ -49,11 +49,11 @@ * Pre-processor Definitions ************************************************************************************/ -/* SPIC Registers *****************************************************************/ +/* SPIC Registers ******************************************************************/ /* Provided in ez80f91.h */ -/* SPIC Register Bit Definitions **************************************************/ +/* SPIC Register Bit Definitions ***************************************************/ /* Baud Rate Generator (BRG) H/L Register Definitions * @@ -97,7 +97,7 @@ extern "C" #endif /* __cplusplus */ /************************************************************************************ - * Public Functions + * Public Function Prototypes ************************************************************************************/ /************************************************************************************ diff --git a/arch/z80/src/ez80/ez80f92.h b/arch/z80/src/ez80/ez80f92.h index c98e07a35f..1d204d7833 100644 --- a/arch/z80/src/ez80/ez80f92.h +++ b/arch/z80/src/ez80/ez80f92.h @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + *********************************************************************************; #ifndef __ARCH_Z80_SRC_EZ80_EZ80F92_H #define __ARCH_Z80_SRC_EZ80_EZ80F92_H /************************************************************************************ * Included Files - ************************************************************************************/ + *********************************************************************************; #include "ez80f91_emac.h" /************************************************************************************ * Pre-processor Definitions - ************************************************************************************/ + *********************************************************************************; -/* Memory map ***********************************************************************/ +/* Memory map ********************************************************************; #define EZ80_ONCHIPFLASH 0x000000 /* CS0: 128Kb of on-chip flash */ #define EZ80_OFFCHIPCS0 0x400000 /* CS0: Off chip use (usually flash) */ @@ -39,13 +39,13 @@ #define EZ80_OFFCHIPCS1 0xc00000 /* CS1: Off chip use (usually SRAM) */ #define EZ80_ONCHIPSRAM 0xffe000 /* On-chip SRAM (8Kb) on reset */ -/* Product ID Registers ************************************************************/ +/* Product ID Registers *********************************************************; #define EZ80_ZDI_ID_L 0x00 #define EZ80_ZDI_ID_H 0x01 #define EZ80_ZDI_ID_REV 0x02 -/* Timer Registers *****************************************************************/ +/* Timer Registers **************************************************************; #define EZ80_TMR0_CTL 0x80 /* RW: Timer 0 control register */ #define EZ80_TMR0_DRL 0x81 /* R : Timer 0 data register (low) */ @@ -85,7 +85,7 @@ #define EZ80_TMR_ISS 0x92 /* Timer input source selection register */ -/* TMR0/1/2/3 CTL Register Bit Definitions *******************************************/ +/* TMR0/1/2/3 CTL Register Bit Definitions ******************************************/ #define EZ80_TMRCTL_IRQ 0x80 /* Bit 7: Generate interrupt request */ #define EZ80_TMRCTL_EN 0x40 /* Bit 6: Enable timer interrupt requests */ @@ -99,12 +99,12 @@ #define EZ80_TMRCTL_RSTEN 0x02 /* Bit 1: Reload and start function enabled */ #define EZ80_TMRCTL_TIMEN 0x01 /* Bit 0: Programmable reload timer enabled */ -/* WDT Registers *********************************************************************/ +/* WDT Registers ********************************************************************/ #define EZ80_WDT_CTL 0x93 #define EZ80_WDT_RR 0x94 -/* GPIO Registers ********************************************************************/ +/* GPIO Registers *******************************************************************/ #define EZ80_PB_DR 0x9a #define EZ80_PB_DDR 0x9b @@ -119,7 +119,7 @@ #define EZ80_PD_ALT1 0xa4 #define EZ80_PD_ALT2 0xa5 -/* CS Registers **********************************************************************/ +/* CS Registers *********************************************************************/ #define EZ80_CS0_LBR 0xa8 #define EZ80_CS0_UBR 0xa9 @@ -134,17 +134,17 @@ #define EZ80_CS3_UBR 0xb2 #define EZ80_CS3_CTL 0xb3 -/* RAMCTL registers ******************************************************************/ +/* RAMCTL registers *****************************************************************/ #define EZ80_RAM_CTL 0xb4 #define EZ80_RAM_ADDR_U 0xb5 -/* RAMCTL bit definitions ************************************************************/ +/* RAMCTL bit definitions ***********************************************************/ #define RAMCTL_ERAMEN (1 << 6) /* Bit 7: 1=On chip EMAC SRAM is enabled */ #define RAMCTL_GPRAMEN (1 << 7) /* Bit 7: 1=On chip GP SRAM is enabled */ -/* SPI Registers *********************************************************************/ +/* SPI Registers ********************************************************************/ #define EZ80_SPI_BRG_L 0xb8 #define EZ80_SPI_BRG_H 0xb9 @@ -153,11 +153,11 @@ #define EZ80_SPI_RBR 0xbc #define EZ80_SPI_TSR 0xbc -/* Infrared Encoder/Decoder Block ****************************************************/ +/* Infrared Encoder/Decoder Block ***************************************************/ #define EZ80_IR_CTL 0xbf /* Infrared Encoder/Decoder Control */ -/* UART Register Offsets *************************************************************/ +/* UART Register Offsets ************************************************************/ /* DLAB=0: */ #define EZ80_UART_THR 0x00 /* W: UART Transmit holding register */ #define EZ80_UART_RBR 0x00 /* R : UART Receive buffer register */