Various SAM4S related fixes, mostely related to the timer driver driver and the SAM4S timer/counter. All from Bob Doisin
This commit is contained in:
Gregory Nutt
parent
df33d9bcc8
commit
61555fe5e1
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@ -7239,4 +7239,7 @@
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Doison (2014-4-21).
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* nuttx/configs/sam4s-xplained-pro: Add board-specific watchdog
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timer support. From Bob Doison (2014-4-21).
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* drivers/timer.c and include/nuttx/timer.h: Timer "upper half"
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driver and lower half interface definition from Bob Doison
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(2014-40-22).
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9
Kconfig
9
Kconfig
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@ -597,6 +597,15 @@ config DEBUG_WATCHDOG
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Support for this debug option is architecture-specific and may not
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be available for some MCUs.
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config DEBUG_TIMER
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bool "Timer Debug Output"
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default n
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depends on TIMER
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---help---
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Enable timer debug SYSLOG output (disabled by default).
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Support for this debug option is architecture-specific and may not
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be available for some MCUs.
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config DEBUG_AUDIO
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bool "Audio Device Debug Output"
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default n
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@ -1214,14 +1214,14 @@ config WDT_DISABLE_ON_RESET
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config WDT_TIMEOUT
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int "Watchdog Timeout (ms)"
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default 4000
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default 5000
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depends on !WDT_DISABLE_ON_RESET
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---help---
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Watchdog timeout value in milliseconds.
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config WDT_MINTIME
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int "Watchdog Minimum Time (ms)"
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default 2000
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default 2500
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depends on !WDT_DISABLE_ON_RESET
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---help---
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Minimum watchdog kick interval
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@ -1239,11 +1239,11 @@ config WDT_THREAD_NAME
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config WDT_THREAD_INTERVAL
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int "Watchdog Thread Interval (ms)"
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default 2000
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default 2500
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config WDT_THREAD_PRIORITY
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int "Watchdog Thread Priority"
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default 99
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default 200
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config WDT_THREAD_STACKSIZE
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int "Watchdog Thread Stacksize"
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@ -137,3 +137,7 @@ endif
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ifeq ($(CONFIG_SAM34_WDT),y)
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CHIP_CSRCS += sam_wdt.c
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endif
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ifeq ($(CONFIG_TIMER),y)
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CHIP_CSRCS += sam_tc.c
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endif
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@ -74,14 +74,15 @@
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#define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
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/* 0x4000c000-0x4000ffff: Reserved */
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#define SAM_TC012_BASE 0x40010000 /* 0x40010000-0x400100bf: Timer Counters 0-2 */
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# define SAM_TC0_BASE 0x40080000 /* 0x40010000-0x4001003f: Timer Counter 0 */
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# define SAM_TC1_BASE 0x40080040 /* 0x40010040-0x4001007f: Timer Counter 1 */
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# define SAM_TC2_BASE 0x40080080 /* 0x40010080-0x400100bf: Timer Counter 2 */
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# define SAM_TC0_BASE 0x40010000 /* 0x40010000-0x4001003f: Timer Counter 0 */
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# define SAM_TC1_BASE 0x40010040 /* 0x40010040-0x4001007f: Timer Counter 1 */
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# define SAM_TC2_BASE 0x40010080 /* 0x40010080-0x400100bf: Timer Counter 2 */
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/* 0x400100c0-0x40013fff Reserved */
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#define SAM_TC345_BASE 0x40080000 /* 0x40014000-0x400140bf: Timer Counters 3-5 */
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# define SAM_TC3_BASE 0x40080000 /* 0x40014000-0x4001403f: Timer Counter 3 */
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# define SAM_TC4_BASE 0x40080040 /* 0x40014040-0x4001407f: Timer Counter 4 */
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# define SAM_TC5_BASE 0x40080080 /* 0x40014080-0x400140bf: Timer Counter 5 */
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#define SAM_TC345_BASE 0x40014000 /* 0x40014000-0x400140bf: Timer Counters 3-5 */
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# define SAM_TC3_BASE 0x40014000 /* 0x40014000-0x4001403f: Timer Counter 3 */
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# define SAM_TC4_BASE 0x40014040 /* 0x40014040-0x4001407f: Timer Counter 4 */
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# define SAM_TC5_BASE 0x40014080 /* 0x40014080-0x400140bf: Timer Counter 5 */
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#define SAM_TWI_BASE 0x40018000 /* 0x40018000-0x4001ffff: Two-Wire Interface */
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# define SAM_TWI0_BASE 0x40018000 /* 0x40018000-0x4001bfff: Two-Wire Interface 0 */
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# define SAM_TWI1_BASE 0x4001c000 /* 0x4001c000-0x4001ffff: Two-Wire Interface 1 */
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@ -296,16 +296,31 @@
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/* Timer common registers */
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#define SAM_TC_BCR (SAM_TC_BASE+SAM_TC_BCR_OFFSET)
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#define SAM_TC_BMR (SAM_TC_BASE+SAM_TC_BMR_OFFSET)
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#define SAM_TC_QIER (SAM_TC_BASE+SAM_TC_QIER_OFFSET)
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#define SAM_TC_QIDR (SAM_TC_BASE+SAM_TC_QIDR_OFFSET)
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#define SAM_TC_QIMR (SAM_TC_BASE+SAM_TC_QIMR_OFFSET)
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#define SAM_TC_QISR (SAM_TC_BASE+SAM_TC_QISR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_TC_FMR (SAM_TC_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC_WPMR (SAM_TC_BASE+SAM_TC_WPMR_OFFSET)
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# define SAM_TC0_BCR (SAM_TC0_BASE+SAM_TC_BCR_OFFSET)
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# define SAM_TC0_BMR (SAM_TC0_BASE+SAM_TC_BMR_OFFSET)
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# define SAM_TC0_QIER (SAM_TC0_BASE+SAM_TC_QIER_OFFSET)
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# define SAM_TC0_QIDR (SAM_TC0_BASE+SAM_TC_QIDR_OFFSET)
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# define SAM_TC0_QIMR (SAM_TC0_BASE+SAM_TC_QIMR_OFFSET)
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# define SAM_TC0_QISR (SAM_TC0_BASE+SAM_TC_QISR_OFFSET)
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# define SAM_TC0_FMR (SAM_TC0_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC0_WPMR (SAM_TC0_BASE+SAM_TC_WPMR_OFFSET)
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# define SAM_TC1_BCR (SAM_TC3_BASE+SAM_TC_BCR_OFFSET)
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# define SAM_TC1_BMR (SAM_TC3_BASE+SAM_TC_BMR_OFFSET)
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# define SAM_TC1_QIER (SAM_TC3_BASE+SAM_TC_QIER_OFFSET)
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# define SAM_TC1_QIDR (SAM_TC3_BASE+SAM_TC_QIDR_OFFSET)
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# define SAM_TC1_QIMR (SAM_TC3_BASE+SAM_TC_QIMR_OFFSET)
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# define SAM_TC1_QISR (SAM_TC3_BASE+SAM_TC_QISR_OFFSET)
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# define SAM_TC1_FMR (SAM_TC3_BASE+SAM_TC_FMR_OFFSET)
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# define SAM_TC1_WPMR (SAM_TC3_BASE+SAM_TC_WPMR_OFFSET)
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#else
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# define SAM_TC_BCR (SAM_TC_BASE+SAM_TC_BCR_OFFSET)
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# define SAM_TC_BMR (SAM_TC_BASE+SAM_TC_BMR_OFFSET)
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# define SAM_TC_QIER (SAM_TC_BASE+SAM_TC_QIER_OFFSET)
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# define SAM_TC_QIDR (SAM_TC_BASE+SAM_TC_QIDR_OFFSET)
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# define SAM_TC_QIMR (SAM_TC_BASE+SAM_TC_QIMR_OFFSET)
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# define SAM_TC_QISR (SAM_TC_BASE+SAM_TC_QISR_OFFSET)
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#endif
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/* TC register bit definitions ******************************************************************/
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@ -393,8 +408,8 @@
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#define TC_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */
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#define TC_CMR_WAVSEL_MASK (3 << TC_CMR_WAVSEL_SHIFT)
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# define TC_CMR_WAVSEL_UP (0 << TC_CMR_WAVSEL_SHIFT) /* UP mode w/o auto trigger (Waveform mode) */
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# define TC_CMR_WAVSEL_UPAUTO (1 << TC_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */
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# define TC_CMR_WAVSEL_UPDWN (2 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */
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# define TC_CMR_WAVSEL_UPDWN (1 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */
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# define TC_CMR_WAVSEL_UPAUTO (2 << TC_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */
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# define TC_CMR_WAVSEL_UPDWNAUTO (3 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */
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#define TC_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */
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#define TC_CMR_ACPA_MASK (3 << TC_CMR_ACPA_SHIFT)
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@ -488,6 +503,9 @@
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define TC_INT_ENDRX (1 << 8) /* Bit 8: End of Receiver Transfer */
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# define TC_INT_RXBUFF (1 << 9) /* Bit 9: Reception Buffer Full */
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# define TC_INT_ALL (TC_INT_COVFS + TC_INT_LOVRS + TC_INT_CPAS + TC_INT_CPBS + TC_INT_CPCS + TC_INT_LDRAS + TC_INT_LDRBS + TC_INT_ETRGS + TC_INT_ENDRX + TC_INT_RXBUFF)
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#else
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# define TC_INT_ALL (TC_INT_COVFS + TC_INT_LOVRS + TC_INT_CPAS + TC_INT_CPBS + TC_INT_CPCS + TC_INT_LDRAS + TC_INT_LDRBS + TC_INT_ETRGS)
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#endif
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#define TC_INT_CLKSTA (1 << 16) /* Bit 16: Clock Enabling (SR only) */
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@ -511,7 +529,7 @@
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/* Timer common registers ***********************************************************************/
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/* TC Block Control Register */
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#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command
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#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command */
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/* TC Block Mode Register */
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@ -387,7 +387,7 @@
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
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# define UART_INT_ALLINTS 0x3f08ffff
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#elif defined(CONFIG_ARCH_CHIP_SAM4S)
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# define UART_INT_ALLINTS 0x010f3fff
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# define UART_INT_ALLINTS 0x010f3fff /* USART - UART only has 0x001AFB? does it matter? */
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#else
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# define UART_INT_ALLINTS 0x01083fff
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#endif
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@ -163,6 +163,7 @@ void up_timerinit(void)
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/* Configure SysTick to interrupt at the requested rate */
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putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
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putreg32(0, NVIC_SYSTICK_CURRENT);
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/* Attach the timer interrupt vector */
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@ -662,6 +662,7 @@ static int sam34_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
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*
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****************************************************************************/
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#ifndef CONFIG_WDT_DISABLE_ON_RESET
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void sam_wdtinitialize(FAR const char *devpath)
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{
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FAR struct sam34_lowerhalf_s *priv = &g_wdgdev;
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@ -696,5 +697,6 @@ void sam_wdtinitialize(FAR const char *devpath)
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(void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
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}
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#endif /* CONFIG_WDT_DISABLE_ON_RESET */
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#endif /* CONFIG_WATCHDOG && CONFIG_SAM34_WDT */
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@ -41,6 +41,7 @@
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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@ -72,6 +72,9 @@ ifeq ($(CONFIG_SAM34_WDT),y)
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CSRCS += sam_wdt.c
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endif
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ifeq ($(CONFIG_TIMER),y)
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CSRCS += sam_tc.c
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endif
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COBJS = $(CSRCS:.c=$(OBJEXT))
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@ -57,7 +57,7 @@
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#define HAVE_HSMCI 1
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#define HAVE_PROC 1
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#define HAVE_USBDEV 1
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#define HAVE_USBDEV 0
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#undef HAVE_USBMONITOR
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/* HSMCI */
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@ -45,10 +45,9 @@
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#include <stdio.h>
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#include <errno.h>
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#include <debug.h>
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#include <unistd.h>
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#ifdef CONFIG_SYSTEM_USBMONITOR
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# include <apps/usbmonitor.h>
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#endif
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#include <nuttx/arch.h>
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#ifdef CONFIG_CDCACM
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# include <nuttx/usb/cdcacm.h>
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@ -58,6 +57,14 @@
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# include <nuttx/usb/pl2303.h>
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#endif
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#ifdef CONFIG_TIMER
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# include <nuttx/timer.h>
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#endif
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#ifdef CONFIG_SYSTEM_USBMONITOR
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# include <apps/usbmonitor.h>
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#endif
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#include "sam4s-xplained-pro.h"
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/****************************************************************************
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@ -134,7 +141,6 @@ int nsh_archinitialize(void)
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}
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#endif
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#warning "add automount config...."
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message("Mounting /dev/mmcsd0 to /fat\n");
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ret = mount("/dev/mmcsd0", "/fat", "vfat", 0, NULL);
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if (ret < 0)
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@ -143,5 +149,11 @@ int nsh_archinitialize(void)
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return ret;
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}
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#ifdef CONFIG_TIMER
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/* Registers the timer driver and starts an async interrupt. */
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up_timerinitialize();
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#endif
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return OK;
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}
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@ -139,6 +139,7 @@ static int wdog_daemon(int argc, char *argv[])
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goto errout_with_dev;
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}
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usleep(200);
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while(1)
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{
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usleep((CONFIG_WDT_THREAD_INTERVAL)*1000);
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@ -247,6 +247,14 @@ config WATCHDOG_DEVPATH
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endif # WATCHDOG
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menuconfig TIMER
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bool "Timer Support"
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default n
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---help---
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This selection enables building of the "upper-half" timer
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driver. See include/nuttx/timer.h for further timer driver
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information.
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menuconfig ANALOG
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bool "Analog Device(ADC/DAC) Support"
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default n
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@ -87,6 +87,10 @@ endif
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ifeq ($(CONFIG_WATCHDOG),y)
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CSRCS += watchdog.c
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endif
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ifeq ($(CONFIG_TIMER),y)
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CSRCS += timer.c
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endif
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endif
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AOBJS = $(ASRCS:.S=$(OBJEXT))
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@ -1,7 +1,7 @@
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/****************************************************************************
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* drivers/timer.c
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -83,7 +83,7 @@
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struct timer_upperhalf_s
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{
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uint8_t crefs; /* The number of times the device has been opened */
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// sem_t exclsem; /* Supports mutual exclusion */
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//sem_t exclsem; /* Supports mutual exclusion */
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FAR char *path; /* Registration path */
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/* The contained lower-half driver */
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@ -114,10 +114,10 @@ static const struct file_operations g_timerops =
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timer_close, /* close */
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timer_read, /* read */
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timer_write, /* write */
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0, /* seek */
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0, /* seek */
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timer_ioctl /* ioctl */
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#ifndef CONFIG_DISABLE_POLL
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, 0 /* poll */
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, 0 /* poll */
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#endif
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};
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@ -155,7 +155,7 @@ static int timer_open(FAR struct file *filep)
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* time that the driver has been opened for this device, then initialize
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* the device.
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*/
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#warning "anythin init to do on first open?"
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tmp = upper->crefs + 1;
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if (tmp == 0)
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{
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@ -230,7 +230,7 @@ errout:
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static ssize_t timer_read(FAR struct file *filep, FAR char *buffer, size_t buflen)
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{
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/* Return zero -- usually meaning end-of-file */
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#warning "return counter value?"
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return 0;
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}
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@ -242,7 +242,8 @@ static ssize_t timer_read(FAR struct file *filep, FAR char *buffer, size_t bufle
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*
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************************************************************************************/
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static ssize_t timer_write(FAR struct file *filep, FAR const char *buffer, size_t buflen)
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static ssize_t timer_write(FAR struct file *filep, FAR const char *buffer,
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size_t buflen)
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{
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return 0;
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}
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@ -287,15 +288,14 @@ static int timer_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
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{
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/* Start the timer, resetting the time to the current timeout */
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//DEBUGASSERT(lower->ops->start); /* Required */
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if(lower->ops->start)
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{
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ret = lower->ops->start(lower);
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}
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else
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{
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if(lower->ops->start)
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{
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ret = lower->ops->start(lower);
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}
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else
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{
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ret = -ENOSYS;
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}
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}
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}
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break;
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@ -308,15 +308,14 @@ static int timer_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
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{
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/* Stop the timer */
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//DEBUGASSERT(lower->ops->stop); /* Required */
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||||
if(lower->ops->start)
|
||||
{
|
||||
ret = lower->ops->stop(lower);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(lower->ops->start)
|
||||
{
|
||||
ret = lower->ops->stop(lower);
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = -ENOSYS;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -353,8 +352,11 @@ static int timer_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
|
|||
/* cmd: TCIOC_SETTIMEOUT
|
||||
* Description: Reset the timeout to this value
|
||||
* Argument: A 32-bit timeout value in microseconds.
|
||||
*
|
||||
* TODO: pass pointer to uint64 ns? Need to determine if these timers
|
||||
* are 16 or 32 bit...
|
||||
*/
|
||||
#warning "TODO - pass pointer to uint64 ns? Need to determine if these timers are 16 or 32 bit..."
|
||||
|
||||
case TCIOC_SETTIMEOUT:
|
||||
{
|
||||
/* Set a new timeout value (and reset the timer) */
|
||||
|
|
|
|||
|
|
@ -70,6 +70,7 @@
|
|||
#define _SLCDIOCBASE (0x1100) /* Segment LCD ioctl commands */
|
||||
#define _WLIOCBASE (0x1200) /* Wireless modules ioctl commands */
|
||||
#define _CFGDIOCBASE (0x1300) /* Config Data device (app config) ioctl commands */
|
||||
#define _TCIOCBASE (0x1400) /* Timer ioctl commands */
|
||||
|
||||
/* Macros used to manage ioctl commands */
|
||||
|
||||
|
|
@ -93,6 +94,11 @@
|
|||
#define _WDIOCVALID(c) (_IOC_TYPE(c)==_WDIOCBASE)
|
||||
#define _WDIOC(nr) _IOC(_WDIOCBASE,nr)
|
||||
|
||||
/* Timer driver ioctl commands *******************************************/
|
||||
|
||||
#define _TCIOCVALID(c) (_IOC_TYPE(c)==_TCIOCBASE)
|
||||
#define _TCIOC(nr) _IOC(_TCIOCBASE,nr)
|
||||
|
||||
/* NuttX file system ioctl definitions **************************************/
|
||||
|
||||
#define _FIOCVALID(c) (_IOC_TYPE(c)==_FIOCBASE)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/****************************************************************************
|
||||
* include/nuttx/timer.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -68,8 +68,11 @@
|
|||
* Argument: A 32-bit timeout value in microseconds.
|
||||
* TCIOC_CAPTURE - Do not reset. Instead, called this handler.
|
||||
* Argument: A pointer to struct timer_capture_s.
|
||||
*
|
||||
* WARNING: May change TCIOC_SETTIMEOUT to pass pointer to 64bit nanoseconds
|
||||
* or timespec structure.
|
||||
*/
|
||||
#warning "may change TCIOC_SETTIMEOUT to pass pointer to 64bit nanoseconds or timespec structure"
|
||||
|
||||
#define TCIOC_START _TCIOC(0x001)
|
||||
#define TCIOC_STOP _TCIOC(0x002)
|
||||
#define TCIOC_GETSTATUS _TCIOC(0x003)
|
||||
|
|
@ -174,7 +177,8 @@ struct timer_lowerhalf_s
|
|||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
|
@ -212,8 +216,8 @@ extern "C" {
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN FAR void *timer_register(FAR const char *path,
|
||||
FAR struct timer_lowerhalf_s *lower);
|
||||
FAR void *timer_register(FAR const char *path,
|
||||
FAR struct timer_lowerhalf_s *lower);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: timer_unregister
|
||||
|
|
@ -230,7 +234,7 @@ EXTERN FAR void *timer_register(FAR const char *path,
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void timer_unregister(FAR void *handle);
|
||||
void timer_unregister(FAR void *handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Platform-Independent "Lower-Half" Timer Driver Interfaces
|
||||
|
|
@ -259,7 +263,7 @@ EXTERN void timer_unregister(FAR void *handle);
|
|||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN int up_timerinitialize(void);
|
||||
int up_timerinitialize(void);
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -209,7 +209,7 @@ int sem_timedwait(FAR sem_t *sem, FAR const struct timespec *abstime)
|
|||
/* Try to take the semaphore without waiting. */
|
||||
|
||||
ret = sem_trywait(sem);
|
||||
if (ret == 0)
|
||||
if (ret == OK)
|
||||
{
|
||||
/* We got it! */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue