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toolchain/ghs: Fix ?? "trigraphs not allowed" warnings 

"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/pci/pci_regs.h", line 263: warning #1695-D:
          trigraphs not allowed
  #define  PCI_PM_CTRL_DATA_SEL_MASK        0x1e00  /* Data select (??) */
                                                                    ^

"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/pci/pci_regs.h", line 264: warning #1695-D:
          trigraphs not allowed
  #define  PCI_PM_CTRL_DATA_SCALE_MASK      0x6000  /* Data scale (??) */
                                                                   ^

"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/pci/pci_regs.h", line 266: warning #1695-D:
          trigraphs not allowed
  #define PCI_PM_PPB_EXTENSIONS             6       /* PPB support extensions (??) */
                                                                               ^

"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/pci/pci_regs.h", line 267: warning #1695-D:
          trigraphs not allowed
  #define  PCI_PM_PPB_B2_B3                 0x40    /* Stop clock when in D3hot (??) */
                                                                                 ^

"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/pci/pci_regs.h", line 268: warning #1695-D:
          trigraphs not allowed
  #define  PCI_PM_BPCC_ENABLE               0x80    /* Bus power/clock control enable (??) */
                                                                                       ^

"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/pci/pci_regs.h", line 269: warning #1695-D:
          trigraphs not allowed
  #define PCI_PM_DATA_REGISTER              7       /* (??) */

Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
This commit is contained in:
yanghuatao 2024-04-23 19:49:32 +08:00 committed by Xiang Xiao
parent e4be747cf5
commit 41d0eaa892
1 changed files with 6 additions and 6 deletions
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12
include/nuttx/pci/pci_regs.h
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@ -267,13 +267,13 @@
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (/?/?) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (/?/?) */
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (/?/?) */
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (/?/?) */
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (/?/?) */
#define PCI_PM_DATA_REGISTER 7 /* (??) */ #define PCI_PM_DATA_REGISTER 7 /* (/?/?) */
#define PCI_PM_SIZEOF 8 #define PCI_PM_SIZEOF 8
/* AGP registers */ /* AGP registers */