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SAM4L: Extend interrupt support for the larger number of NVIC interrupts of the SAM4L

This commit is contained in:
Gregory Nutt 2013-06-09 13:00:38 -06:00
parent 3eefc08c12
commit 3938eeeb96
6 changed files with 134 additions and 22 deletions
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4
ChangeLog
View File

@ -4935,4 +4935,6 @@
* configs/sam4l-xplained/nsh: Added an NSH configuration for the
SAM4L Xplained Pro board (2013-6-9).
* configs/sam4l-xplained/src/sam_cxxinitialize.c: Added C++ support
to the SAM4L Xplained Pro board configuration (2013-6-9).
to the SAM4L Xplained Pro board configuration (2013-6-9).
* arm/src/sam34/chip/sam_irq.c: Extend IRQ support to handle the
larger number of NVIC interrupts used by the SAM4L (2013-6-9).

57
Documentation/NuttX.html
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@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: May 29, 2013</p>
<p>Last Updated: June 9, 2013</p>
</td>
</tr>
</table>
@ -1578,7 +1578,7 @@
<li><a href="#arm926ejs">ARM926EJS</a> (3) </li>
<li><a href="#armcortexm0">ARM Cortex-M0/M0+</a> (2)</li>
<li><a href="#armcortexm3">ARM Cortex-M3</a> (19)</li>
<li><a href="#armcortexm4">ARM Cortex-M4</a> (7)</li>
<li><a href="#armcortexm4">ARM Cortex-M4</a> (8)</li>
</ul>
<li>Atmel AVR
<ul>
@ -1640,6 +1640,7 @@
<li><a href="#avrat90usbxxx">AVR AT90USB64x and AT90USB6128x</a> <small>(8-bit AVR)</small></li>
<li><a href="#at32uc3bxxx">AVR32 AT32UC3BXXX</a> <small>(32-bit AVR32)</small></li>
<li><a href="#at91sam3u">Atmel AT91SAM3U</a> <small>(ARM Cortex-M3)</small></li>
<li><a href="#at91sam4l">Atmel AT91SAM4L</a> <small>(ARM Cortex-M4)</small></li>
</ul>
</li>
<li>Freescale
@ -2950,7 +2951,7 @@ nsh>
<ul>
<p>
<b>STATUS:</b>
As of this writing, the basic port is code complete and fully verified configurations exit for the basic NuttX OS test and for the NuttShell <a href="http://www.nuttx.org/Documentation/NuttShell.html">NSH</a>).
As of this writing, the basic port is code complete and fully verified configurations exist for the basic NuttX OS test and for the NuttShell <a href="http://www.nuttx.org/Documentation/NuttShell.html">NSH</a>).
The first fully functional LM4F120 LaunchPad port was released in NuttX-6.27.
</p>
</ul>
@ -2960,6 +2961,56 @@ nsh>
<td><br></td>
<td><hr></td>
</tr>
<tr>
<td><br></td>
<td>
<p>
<a name="at91sam4l"><b>Atmel AT91SAM4L</b>.</a>
This port uses the Atmel SAM4L Xplained Pro development board.
This board features the ATSAM4LC4C MCU with 256KB of FLASH and 32KB of internal SRAM.
</p>
<ul>
<p>
<b>STATUS:</b>
As of this writing, the basic port is code complete and fully verified configurations exist for the basic NuttX OS test and for the NuttShell <a href="http://www.nuttx.org/Documentation/NuttShell.html">NSH</a>).
The first fully functional LM4F120 LaunchPad port was released in NuttX-6.28.
</p>
<p>
<b>Memory Usage</b>.
The ATSAM4LC4C comes in a 61004-pin package and has 256KB FLASH and 32KB of SRAM.
Below is the current memory usage for the NSH configuration (June 9, 2013).
This is <i>not</i> a minimal implementation, but a full-featured NSH configuration.
</p>
<p>
Static memory usage can be shown with <code>size</code> command:
</p>
<ul><pre>
$ size nuttx
text data bss dec hex filename
43572 122 2380 46074 b3fa nuttx
</pre></ul>
<p>
NuttX, the NSH application, and GCC libraries use 42.6KB of FLASH leaving 213.4B of FLASH (83.4%) free from additional application development.
Static SRAM usage is about 2.3KB (&lt;7%) and leaves 29.7KB (92.7%) available for heap at runtime.
</p>
SRAM usage at run-time can be shown with the NSH <code>free</code> command.
This runtime memory usage includes the static memory usage <i>plus</i> all dynamic memory allocation for things like stacks and I/O buffers:
<ul><pre>
NuttShell (NSH) NuttX-6.28
nsh> free
total used free largest
Mem: 29232 5920 23312 23312
</pre></ul>
<p>
You can see that 22.8KB (71.1%) of the SRAM heap is staill available for further application development while NSH is running.
</p>
</ul>
</td>
</tr>
<tr>
<td><br></td>
<td><hr></td>
</tr>
<tr>
<td><br></td>
<td>

4
arch/arm/src/armv7-m/nvic.h
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@ -399,8 +399,8 @@
/* Interrrupt controller type (INCTCTL_TYPE) */
#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 4-0: Number of interrupt intputs / 32 */
#define NVIC_ICTR_INTLINESNUM_MASK (0x1f << NVIC_ICTR_INTLINESNUM_SHIFT)
#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 0-3: Number of interrupt inputs / 32 - 1 */
#define NVIC_ICTR_INTLINESNUM_MASK (15 << NVIC_ICTR_INTLINESNUM_SHIFT)
/* SysTick control and status register (SYSTICK_CTRL) */

86
arch/arm/src/sam34/sam_irq.c
View File

@ -221,18 +221,51 @@ static inline void sam_prioritize_syscall(int priority)
static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
{
unsigned int extint = irq - SAM_IRQ_EXTINT;
DEBUGASSERT(irq >= SAM_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= SAM_IRQ_EXTINT)
{
if (irq < SAM_IRQ_NIRQS)
#if SAM_IRQ_NEXTINT <= 32
if (extint < SAM_IRQ_NEXTINT)
{
*regaddr = NVIC_IRQ0_31_ENABLE;
*bit = 1 << (irq - SAM_IRQ_EXTINT);
*bit = 1 << extint;
}
else
#elif SAM_IRQ_NEXTINT <= 64
if (extint < 32)
{
*regaddr = NVIC_IRQ0_31_ENABLE;
*bit = 1 << extint;
}
else if (extint < SAM_IRQ_NEXTINT)
{
*regaddr = NVIC_IRQ32_63_ENABLE;
*bit = 1 << (extint - 32);
}
else
#elif SAM_IRQ_NEXTINT <= 96
if (extint < 32)
{
*regaddr = NVIC_IRQ0_31_ENABLE;
*bit = 1 << extint;
}
else if (extint < 64)
{
*regaddr = NVIC_IRQ32_63_ENABLE;
*bit = 1 << (extint - 32);
}
else if (extint < SAM_IRQ_NEXTINT)
{
*regaddr = NVIC_IRQ64_95_ENABLE;
*bit = 1 << (extint - 64);
}
else
#endif
{
return ERROR; /* Invalid interrupt */
}
@ -279,9 +312,32 @@ static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
void up_irqinitialize(void)
{
/* Disable all interrupts */
uintptr_t regaddr;
int nintlines;
int i;
putreg32(0, NVIC_IRQ0_31_ENABLE);
/* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
* lines that the NVIC supports, defined in groups of 32. That is,
* the total number of interrupt lines is up to (32*(INTLINESNUM+1)).
*
* 0 -> 32 interrupt lines, 1 enable register, 8 priority registers
* 1 -> 64 " " " ", 2 enable registers, 16 priority registers
* 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers
* ...
*/
nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1;
/* Disable all interrupts. There are nintlines interrupt enable
* registers.
*/
for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE;
i > 0;
i--, regaddr += 4)
{
putreg32(0, regaddr);
}
/* Set up the vector table address.
*
@ -291,24 +347,26 @@ void up_irqinitialize(void)
#if defined(CONFIG_ARCH_RAMVECTORS)
up_ramvec_initialize();
#elif defined(CONFIG_STM32_DFU)
#elif defined(CONFIG_SAM_BOOTLOADER)
putreg32((uint32_t)sam_vectors, NVIC_VECTAB);
#endif
/* Set all interrrupts (and exceptions) to the default priority */
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
/* Now set all of the interrupt lines to the default priority. There are
* nintlines * 8 priority registers.
*/
for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY;
i > 0;
i--, regaddr += 4)
{
putreg32(0, regaddr);
}
/* currents_regs is non-NULL only while processing an interrupt */

1
arch/arm/src/sam34/sam_serial.c
View File

@ -1310,6 +1310,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
priv->imr &= ~UART_INT_TXRDY;
up_disableint(priv);
}
irqrestore(flags);
}

4
configs/sam4l-xplained/scripts/ld.script
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@ -33,8 +33,8 @@
*
****************************************************************************/
/* The ATSAM4LC4C has 256Kb of FLASH beginning at address 0x0000:0000 and
* 32Kb of SRAM beginning at address 0x2000:0000
/* The ATSAM4LC4C has 256KB of FLASH beginning at address 0x0000:0000 and
* 32KB of SRAM beginning at address 0x2000:0000
*/
MEMORY