From 3938eeeb963eb08ee909d9cb746f86e7c865047c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 9 Jun 2013 13:00:38 -0600 Subject: [PATCH] SAM4L: Extend interrupt support for the larger number of NVIC interrupts of the SAM4L --- ChangeLog | 4 +- Documentation/NuttX.html | 57 +++++++++++++++- arch/arm/src/armv7-m/nvic.h | 4 +- arch/arm/src/sam34/sam_irq.c | 86 ++++++++++++++++++++---- arch/arm/src/sam34/sam_serial.c | 1 + configs/sam4l-xplained/scripts/ld.script | 4 +- 6 files changed, 134 insertions(+), 22 deletions(-) diff --git a/ChangeLog b/ChangeLog index 8fa2df4407..c3e8420432 100644 --- a/ChangeLog +++ b/ChangeLog @@ -4935,4 +4935,6 @@ * configs/sam4l-xplained/nsh: Added an NSH configuration for the SAM4L Xplained Pro board (2013-6-9). * configs/sam4l-xplained/src/sam_cxxinitialize.c: Added C++ support - to the SAM4L Xplained Pro board configuration (2013-6-9). \ No newline at end of file + to the SAM4L Xplained Pro board configuration (2013-6-9). + * arm/src/sam34/chip/sam_irq.c: Extend IRQ support to handle the + larger number of NVIC interrupts used by the SAM4L (2013-6-9). \ No newline at end of file diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index c8922cf36a..cfa518a64b 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -8,7 +8,7 @@

NuttX RTOS

-

Last Updated: May 29, 2013

+

Last Updated: June 9, 2013

@@ -1578,7 +1578,7 @@
  • ARM926EJS (3)
  • ARM Cortex-M0/M0+ (2)
  • ARM Cortex-M3 (19)
    • -
  • ARM Cortex-M4 (7)
    • +
  • ARM Cortex-M4 (8)
  • Atmel AVR
  • Freescale @@ -2950,7 +2951,7 @@ nsh> @@ -2960,6 +2961,56 @@ nsh>
    + +
    + +

    + Atmel AT91SAM4L. + This port uses the Atmel SAM4L Xplained Pro development board. + This board features the ATSAM4LC4C MCU with 256KB of FLASH and 32KB of internal SRAM. +

    + + + + +
    +
    +
    diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h index e6d6f8e9e1..2d76e4e6b6 100644 --- a/arch/arm/src/armv7-m/nvic.h +++ b/arch/arm/src/armv7-m/nvic.h @@ -399,8 +399,8 @@ /* Interrrupt controller type (INCTCTL_TYPE) */ -#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 4-0: Number of interrupt intputs / 32 */ -#define NVIC_ICTR_INTLINESNUM_MASK (0x1f << NVIC_ICTR_INTLINESNUM_SHIFT) +#define NVIC_ICTR_INTLINESNUM_SHIFT 0 /* Bits 0-3: Number of interrupt inputs / 32 - 1 */ +#define NVIC_ICTR_INTLINESNUM_MASK (15 << NVIC_ICTR_INTLINESNUM_SHIFT) /* SysTick control and status register (SYSTICK_CTRL) */ diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index f212742114..dcb6a187c7 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -221,18 +221,51 @@ static inline void sam_prioritize_syscall(int priority) static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) { + unsigned int extint = irq - SAM_IRQ_EXTINT; + DEBUGASSERT(irq >= SAM_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ if (irq >= SAM_IRQ_EXTINT) { - if (irq < SAM_IRQ_NIRQS) +#if SAM_IRQ_NEXTINT <= 32 + if (extint < SAM_IRQ_NEXTINT) { *regaddr = NVIC_IRQ0_31_ENABLE; - *bit = 1 << (irq - SAM_IRQ_EXTINT); + *bit = 1 << extint; } else +#elif SAM_IRQ_NEXTINT <= 64 + if (extint < 32) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << extint; + } + else if (extint < SAM_IRQ_NEXTINT) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (extint - 32); + } + else +#elif SAM_IRQ_NEXTINT <= 96 + if (extint < 32) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << extint; + } + else if (extint < 64) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (extint - 32); + } + else if (extint < SAM_IRQ_NEXTINT) + { + *regaddr = NVIC_IRQ64_95_ENABLE; + *bit = 1 << (extint - 64); + } + else +#endif { return ERROR; /* Invalid interrupt */ } @@ -279,9 +312,32 @@ static int sam_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit) void up_irqinitialize(void) { - /* Disable all interrupts */ + uintptr_t regaddr; + int nintlines; + int i; - putreg32(0, NVIC_IRQ0_31_ENABLE); + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_ENABLE; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } /* Set up the vector table address. * @@ -291,24 +347,26 @@ void up_irqinitialize(void) #if defined(CONFIG_ARCH_RAMVECTORS) up_ramvec_initialize(); -#elif defined(CONFIG_STM32_DFU) +#elif defined(CONFIG_SAM_BOOTLOADER) putreg32((uint32_t)sam_vectors, NVIC_VECTAB); #endif - /* Set all interrrupts (and exceptions) to the default priority */ + /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); - putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ + + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(0, regaddr); + } /* currents_regs is non-NULL only while processing an interrupt */ diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c index 713326e07c..f2289d356d 100644 --- a/arch/arm/src/sam34/sam_serial.c +++ b/arch/arm/src/sam34/sam_serial.c @@ -1310,6 +1310,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable) priv->imr &= ~UART_INT_TXRDY; up_disableint(priv); } + irqrestore(flags); } diff --git a/configs/sam4l-xplained/scripts/ld.script b/configs/sam4l-xplained/scripts/ld.script index e908e7a3ee..7a225b9991 100755 --- a/configs/sam4l-xplained/scripts/ld.script +++ b/configs/sam4l-xplained/scripts/ld.script @@ -33,8 +33,8 @@ * ****************************************************************************/ -/* The ATSAM4LC4C has 256Kb of FLASH beginning at address 0x0000:0000 and - * 32Kb of SRAM beginning at address 0x2000:0000 +/* The ATSAM4LC4C has 256KB of FLASH beginning at address 0x0000:0000 and + * 32KB of SRAM beginning at address 0x2000:0000 */ MEMORY