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Merged in david_s5/nuttx/px4_firmware_nuttx-8.1+_bbsram_mpu (pull request #1069) 

STM32H7:Set the BBSRAM memory range to non-cacheable.

* armv7-m:mpu add user peripheral helper

* stm32h7:BBSRAM Exclude BBSRAM from cacheable when CONFIG_ARMV7M_DCACHE

       ST placed the STM32H7 BBSRAM in the SRAM default memory region
       which is cacheable. This commit sets the BBSRAM memory range
       to non-cacheable.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
David Sidrane 2019-11-08 16:17:28 +00:00 committed by Gregory Nutt
parent 2b8cd24364
commit 2213904cfd
3 changed files with 61 additions and 2 deletions
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44
arch/arm/src/armv7-m/mpu.h
View File

@ -259,7 +259,6 @@ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena)
putreg32(regval, MPU_CTRL);
}
/****************************************************************************
* Name: mpu_priv_stronglyordered
*
@ -538,7 +537,7 @@ static inline void mpu_priv_extsram(uintptr_t base, size_t size)
* Name: mpu_peripheral
*
* Description:
* Configure a region as privileged periperal address space
* Configure a region as privileged peripheral address space
*
****************************************************************************/
@ -575,6 +574,47 @@ static inline void mpu_peripheral(uintptr_t base, size_t size)
putreg32(regval, MPU_RASR);
}
/****************************************************************************
* Name: mpu_user_peripheral
*
* Description:
* Configure a region as user peripheral address space
*
****************************************************************************/
static inline void mpu_user_peripheral(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
uint32_t regval;
uint8_t l2size;
uint8_t subregions;
/* Select the region */
putreg32(region, MPU_RNR);
/* Select the region base address */
putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR);
/* Select the region size and the sub-region map */
l2size = mpu_log2regionceil(size);
subregions = mpu_subregion(base, size, l2size);
/* Then configure the region */
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */
((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */
MPU_RASR_S | /* Shareable */
MPU_RASR_B | /* Bufferable */
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_XN; /* Instruction access disable */
putreg32(regval, MPU_RASR);
}
#undef EXTERN
#if defined(__cplusplus)
}

5
arch/arm/src/stm32h7/Make.defs
View File

@ -129,6 +129,11 @@ CHIP_CSRCS += stm32_adc.c
endif
ifeq ($(CONFIG_STM32H7_BBSRAM),y)
ifeq ($(CONFIG_ARMV7M_DCACHE),y)
ifeq ($(CONFIG_BUILD_PROTECTED),)
CMN_CSRCS += up_mpu.c
endif
endif
CHIP_CSRCS += stm32_bbsram.c
endif

14
arch/arm/src/stm32h7/stm32_bbsram.c
View File

@ -59,6 +59,7 @@
#include "stm32_bbsram.h"
#include "chip.h"
#include "mpu.h"
#include "stm32_pwr.h"
#ifdef CONFIG_STM32H7_BBSRAM
@ -806,6 +807,19 @@ int stm32_bbsraminitialize(char *devpath, int *sizes)
return -EINVAL;
}
#if defined(CONFIG_ARMV7M_DCACHE)
/* ST placed the H7's BBSRAM in the default region for SRAM so we need to
* make it not cacheable
*/
# if defined(CONFIG_BUILD_PROTECTED)
mpu_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE);
# else
mpu_user_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE);
mpu_control(true, true, true);
# endif
#endif
memset(g_bbsram, 0, sizeof(g_bbsram));
/* Clocking for the PWR block must be provided. However, this is done