From 2213904cfd3c7e9672295ae4023cc467a09c2b4e Mon Sep 17 00:00:00 2001
From: David Sidrane <david.sidrane@nscdg.com>
Date: Fri, 8 Nov 2019 16:17:28 +0000
Subject: [PATCH] Merged in david_s5/nuttx/px4_firmware_nuttx-8.1+_bbsram_mpu
 (pull request #1069)

STM32H7:Set the BBSRAM memory range to non-cacheable.

* armv7-m:mpu add user peripheral helper

* stm32h7:BBSRAM Exclude BBSRAM from cacheable when CONFIG_ARMV7M_DCACHE

       ST placed the STM32H7 BBSRAM in the SRAM default memory region
       which is cacheable. This commit sets the BBSRAM memory range
       to non-cacheable.

Approved-by: Gregory Nutt <gnutt@nuttx.org>
---
 arch/arm/src/armv7-m/mpu.h          | 44 +++++++++++++++++++++++++++--
 arch/arm/src/stm32h7/Make.defs      |  5 ++++
 arch/arm/src/stm32h7/stm32_bbsram.c | 14 +++++++++
 3 files changed, 61 insertions(+), 2 deletions(-)

diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h
index 9551d765b1..1642f7df8c 100644
--- a/arch/arm/src/armv7-m/mpu.h
+++ b/arch/arm/src/armv7-m/mpu.h
@@ -259,7 +259,6 @@ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena)
   putreg32(regval, MPU_CTRL);
 }
 
-
 /****************************************************************************
  * Name: mpu_priv_stronglyordered
  *
@@ -538,7 +537,7 @@ static inline void mpu_priv_extsram(uintptr_t base, size_t size)
  * Name: mpu_peripheral
  *
  * Description:
- *   Configure a region as privileged periperal address space
+ *   Configure a region as privileged peripheral address space
  *
  ****************************************************************************/
 
@@ -575,6 +574,47 @@ static inline void mpu_peripheral(uintptr_t base, size_t size)
   putreg32(regval, MPU_RASR);
 }
 
+/****************************************************************************
+ * Name: mpu_user_peripheral
+ *
+ * Description:
+ *   Configure a region as user peripheral address space
+ *
+ ****************************************************************************/
+
+static inline void mpu_user_peripheral(uintptr_t base, size_t size)
+{
+  unsigned int region = mpu_allocregion();
+  uint32_t     regval;
+  uint8_t      l2size;
+  uint8_t      subregions;
+
+  /* Select the region */
+
+  putreg32(region, MPU_RNR);
+
+  /* Select the region base address */
+
+  putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR);
+
+  /* Select the region size and the sub-region map */
+
+  l2size     = mpu_log2regionceil(size);
+  subregions = mpu_subregion(base, size, l2size);
+
+  /* Then configure the region */
+
+  regval = MPU_RASR_ENABLE                              | /* Enable region */
+           MPU_RASR_SIZE_LOG2((uint32_t)l2size)         | /* Region size   */
+           ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions   */
+           MPU_RASR_S                                   | /* Shareable     */
+           MPU_RASR_B                                   | /* Bufferable    */
+           MPU_RASR_AP_RWRW                             | /* P:RW   U:RW */
+           MPU_RASR_XN;                                   /* Instruction access disable */
+
+  putreg32(regval, MPU_RASR);
+}
+
 #undef EXTERN
 #if defined(__cplusplus)
 }
diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs
index 7074c2e938..5a132304c0 100644
--- a/arch/arm/src/stm32h7/Make.defs
+++ b/arch/arm/src/stm32h7/Make.defs
@@ -129,6 +129,11 @@ CHIP_CSRCS += stm32_adc.c
 endif
 
 ifeq ($(CONFIG_STM32H7_BBSRAM),y)
+ifeq ($(CONFIG_ARMV7M_DCACHE),y)
+ifeq ($(CONFIG_BUILD_PROTECTED),)
+CMN_CSRCS += up_mpu.c
+endif
+endif
 CHIP_CSRCS += stm32_bbsram.c
 endif
 
diff --git a/arch/arm/src/stm32h7/stm32_bbsram.c b/arch/arm/src/stm32h7/stm32_bbsram.c
index 6a4f0a22dc..f5830d715b 100644
--- a/arch/arm/src/stm32h7/stm32_bbsram.c
+++ b/arch/arm/src/stm32h7/stm32_bbsram.c
@@ -59,6 +59,7 @@
 
 #include "stm32_bbsram.h"
 #include "chip.h"
+#include "mpu.h"
 #include "stm32_pwr.h"
 
 #ifdef CONFIG_STM32H7_BBSRAM
@@ -806,6 +807,19 @@ int stm32_bbsraminitialize(char *devpath, int *sizes)
       return -EINVAL;
     }
 
+#if defined(CONFIG_ARMV7M_DCACHE)
+  /* ST placed the H7's BBSRAM in the default region for SRAM so we need to
+   * make it not cacheable
+   */
+
+#  if defined(CONFIG_BUILD_PROTECTED)
+  mpu_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE);
+#  else
+  mpu_user_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE);
+  mpu_control(true, true, true);
+#  endif
+#endif
+
   memset(g_bbsram, 0, sizeof(g_bbsram));
 
   /* Clocking for the PWR block must be provided.  However, this is done