arm64/imx9: Add register definitions for LPTMR
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Ville Juven
Xiang Xiao
parent
0b8f6af3d6
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00986bdd09
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/****************************************************************************
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* arch/arm64/src/imx9/hardware/imx9_lptmr.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_
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#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define IMX9_LPTMR_CSR_OFFSET 0x0000 /* Control Status */
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#define IMX9_LPTMR_PSR_OFFSET 0x0004 /* Prescale */
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#define IMX9_LPTMR_CMR_OFFSET 0x0008 /* Compare */
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#define IMX9_LPTMR_CNR_OFFSET 0x000c /* Counter */
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/* Register Address *********************************************************/
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#define LPTMR_CSR(n) ((n) + IMX9_LPTMR_CSR_OFFSET)
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#define LPTMR_PSR(n) ((n) + IMX9_LPTMR_PSR_OFFSET)
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#define LPTMR_CMR(n) ((n) + IMX9_LPTMR_CMR_OFFSET)
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#define LPTMR_CNR(n) ((n) + IMX9_LPTMR_CNR_OFFSET)
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/* Register Bitfield Definitions ********************************************/
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#define LPTMR_CSR_TDRE (1 << 8) /* Timer DMA Request Enable */
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#define LPTMR_CSR_TCF (1 << 7) /* Timer Compare Flag */
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#define LPTMR_CSR_TIE (1 << 6) /* Timer Interrupt Enable */
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#define LPTMR_CSR_TPS_SHIFT (4) /* Bit[5:4]: Timer Pin Select */
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#define LPTMR_CSR_TPS_MASK (3 << LPTMR_CSR_TPS_SHIFT)
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#define LPTMR_CSR_TPS0 (0 << LPTMR_CSR_TPS_SHIFT)
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#define LPTMR_CSR_TPS1 (1 << LPTMR_CSR_TPS_SHIFT)
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#define LPTMR_CSR_TPS2 (2 << LPTMR_CSR_TPS_SHIFT)
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#define LPTMR_CSR_TPS3 (3 << LPTMR_CSR_TPS_SHIFT)
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#define LPTMR_CSR_TPP (1 << 3) /* Timer Pin Polarity */
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#define LPTMR_CSR_TFC (1 << 2) /* Timer Free-Running Counter */
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#define LPTMR_CSR_TMS (1 << 1) /* Timer Mode Select */
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#define LPTMR_CSR_TEN (1 << 0) /* Timer Enable */
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#define LPTMR_PSR_PRESCALE_SHIFT (3) /* Bit[6:3]: Prescale Value */
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#define LPTMR_PSR_PRESCALE_MASK (0xf << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV2 (0 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV4 (1 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV8 (2 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV16 (3 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV32 (4 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV64 (5 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV128 (6 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV256 (7 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV512 (8 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV1024 (9 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV2048 (10 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV4096 (11 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV8192 (12 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV16384 (13 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV32768 (14 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PRESCALE_DIV65536 (15 << LPTMR_PSR_PRESCALE_SHIFT)
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#define LPTMR_PSR_PBYP (1 << 2) /* Prescaler Bypass */
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/* Clock sources (module clock / root clock)
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* ipg_clk_irclk -> lptmrx_clk_root
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* ipg_clk_1khz -> 32k_clk_root
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* ipg_clk_32khz -> 32k_clk_root
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* ipg_clk_ercl -> 32k_clk_root
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*/
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#define LPTMR_PSR_PCS_SHIFT (0) /* Bit[1:0]: Prescaler Clock Select */
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#define LPTMR_PSR_PCS_MASK (3 << LPTMR_PSR_PCS_SHIFT)
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#define LPTMR_PSR_PCS_REF_INT (0 << LPTMR_PSR_PCS_SHIFT) /* Internal reference clock */
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#define LPTMR_PSR_PCS_LPO (1 << LPTMR_PSR_PCS_SHIFT) /* LPO 1K Hz */
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#define LPTMR_PSR_PCS_RTC (2 << LPTMR_PSR_PCS_SHIFT) /* RTC 32768 Hz */
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#define LPTMR_PSR_PCS_REF_EXT (3 << LPTMR_PSR_PCS_SHIFT) /* External reference clock */
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# define LPTMR_PSR_PCS_SOSC LPTMR_PSR_PCS_RFOSC
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#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_ */
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