arm64/imx9: Add register definitions for LPIT
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Ville Juven
Xiang Xiao
parent
d2373f4569
commit
0b8f6af3d6
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/****************************************************************************
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* arch/arm64/src/imx9/hardware/imx9_lpit.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPIT_H
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#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPIT_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define IMX9_LPIT_VERID_OFFSET 0x0000 /* Version ID */
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#define IMX9_LPIT_PARAM_OFFSET 0x0004 /* Parameter */
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#define IMX9_LPIT_MCR_OFFSET 0x0008 /* Module Control */
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#define IMX9_LPIT_MSR_OFFSET 0x000c /* Module Status Register */
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#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Moduel Interrupt Enable */
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#define IMX9_LPIT_SETTEN_OFFSET 0x0014 /* Set Timer Enable */
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#define IMX9_LPIT_CLRTEN_OFFSET 0x0018 /* Clear Timer Enable */
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#define IMX9_LPIT_TVAL0_OFFSET 0x0020 /* Timer Channel 0 Value */
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#define IMX9_LPIT_CVAL0_OFFSET 0x0024 /* Current Timer Channel 0 Value */
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#define IMX9_LPIT_TCTRL0_OFFSET 0x0028 /* Timer Channel 0 Control */
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#define IMX9_LPIT_TVAL1_OFFSET 0x0030 /* Timer Channel 1 Value */
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#define IMX9_LPIT_CVAL1_OFFSET 0x0034 /* Current Timer Channel 1 Value */
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#define IMX9_LPIT_TCTRL1_OFFSET 0x0048 /* Timer Channel 1 Control */
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#define IMX9_LPIT_TVAL2_OFFSET 0x0040 /* Timer Channel 2 Value */
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#define IMX9_LPIT_CVAL2_OFFSET 0x0044 /* Current Timer Channel 2 Value */
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#define IMX9_LPIT_TCTRL2_OFFSET 0x0048 /* Timer Channel 2 Control */
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#define IMX9_LPIT_TVAL3_OFFSET 0x0050 /* Timer Channel 3 Value */
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#define IMX9_LPIT_CVAL3_OFFSET 0x0054 /* Current Timer Channel 3 Value */
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#define IMX9_LPIT_TCTRL3_OFFSET 0x0058 /* Timer Channel 3 Control */
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/* Register access */
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#define LPIT_VERID(n) ((n) + IMX9_LPIT_VERID_OFFSET)
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#define LPIT_PARAM(n) ((n) + IMX9_LPIT_PARAM_OFFSET)
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#define LPIT_MCR(n) ((n) + IMX9_LPIT_MCR_OFFSET)
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#define LPIT_MSR(n) ((n) + IMX9_LPIT_MSR_OFFSET)
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#define LPIT_MIER(n) ((n) + IMX9_LPIT_MIER_OFFSET)
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#define LPIT_SETTEN(n) ((n) + IMX9_LPIT_SETTEN_OFFSET)
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#define LPIT_CLRTEN(n) ((n) + IMX9_LPIT_CLRTEN_OFFSET)
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#define LPIT_TVAL0(n) ((n) + IMX9_LPIT_TVAL0_OFFSET)
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#define LPIT_CVAL0(n) ((n) + IMX9_LPIT_CVAL0_OFFSET)
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#define LPIT_TCTRL0(n) ((n) + IMX9_LPIT_TCTRL0_OFFSET)
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#define LPIT_TVAL1(n) ((n) + IMX9_LPIT_TVAL1_OFFSET)
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#define LPIT_CVAL1(n) ((n) + IMX9_LPIT_CVAL1_OFFSET)
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#define LPIT_TCTRL1(n) ((n) + IMX9_LPIT_TCTRL1_OFFSET)
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#define LPIT_TVAL2(n) ((n) + IMX9_LPIT_TVAL2_OFFSET)
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#define LPIT_CVAL2(n) ((n) + IMX9_LPIT_CVAL2_OFFSET)
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#define LPIT_TCTRL2(n) ((n) + IMX9_LPIT_TCTRL2_OFFSET)
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#define LPIT_TVAL3(n) ((n) + IMX9_LPIT_TVAL3_OFFSET)
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#define LPIT_CVAL3(n) ((n) + IMX9_LPIT_CVAL3_OFFSET)
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#define LPIT_TCTRL3(n) ((n) + IMX9_LPIT_TCTRL3_OFFSET)
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/* Register Bitfield Definitions ********************************************/
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#define LPIT_PARAM_EXT_TRIG_SHIFT (8) /* Bit[15:8]: Number of External Trigger Inputs */
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#define LPIT_PARAM_EXT_TRIG_MASK (0xff << LPIT_PARAM_EXT_TRIG_SHIFT)
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#define LPIT_PARAM_CHANNEL_SHIFT (0) /* Bit[7:0]: Number of Timer Channels */
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#define LPIT_PARAM_CHANNEL_MASK (0xff << LPIT_PARAM_CHANNEL_SHIFT)
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#define LPIT_MCR_DBG_EN (1 << 3) /* Stop Timer when in Debug Mode */
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#define LPIT_MCR_DOZE_EN (1 << 2) /* DOZE Mode Enable */
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#define LPIT_MCR_SW_RST (1 << 1) /* Software Reset Bit */
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#define LPIT_MCR_M_CEN (1 << 0) /* Module Clock Enable */
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#define LPIT_MSR_TIF3 (1 << 3) /* Channel 3 Timer Interrupt Flag */
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#define LPIT_MSR_TIF2 (1 << 2) /* Channel 2 Timer Interrupt Flag */
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#define LPIT_MSR_TIF1 (1 << 1) /* Channel 1 Timer Interrupt Flag */
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#define LPIT_MSR_TIF0 (1 << 0) /* Channel 0 Timer Interrupt Flag */
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#define LPIT_MIER_TIE3 (1 << 3) /* Channel 3 Timer Interrupt Enable */
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#define LPIT_MIER_TIE2 (1 << 2) /* Channel 2 Timer Interrupt Enable */
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#define LPIT_MIER_TIE1 (1 << 1) /* Channel 1 Timer Interrupt Enable */
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#define LPIT_MIER_TIE0 (1 << 0) /* Channel 0 Timer Interrupt Enable */
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#define LPIT_TCTRL_TRG_SEL_SHIFT (27) /* Bit[27:24]: Trigger Select */
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#define LPIT_TCTRL_TRG_SEL_MASK (0xf << LPIT_TCTRL_TRG_SEL_SHIFT)
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#define LPIT_TCTRL_TRG_SEL_CHAN0 (0 << LPIT_TCTRL_TRG_SEL_SHIFT)
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#define LPIT_TCTRL_TRG_SEL_CHAN1 (1 << LPIT_TCTRL_TRG_SEL_SHIFT)
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#define LPIT_TCTRL_TRG_SEL_CHAN2 (2 << LPIT_TCTRL_TRG_SEL_SHIFT)
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#define LPIT_TCTRL_TRG_SEL_CHAN3 (3 << LPIT_TCTRL_TRG_SEL_SHIFT)
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#define LPIT_TCTRL_TRG_SRC_SHIFT (23) /* Bit23: Trigger Source */
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#define LPIT_TCTRL_TRG_SRC_MASK (1 << LPIT_TCTRL_TRG_SRC_SHIFT)
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#define LPIT_TCTRL_TRG_SRC_EXTER (0 << LPIT_TCTRL_TRG_SRC_SHIFT) /* external */
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#define LPIT_TCTRL_TRG_SRC_INTER (1 << LPIT_TCTRL_TRG_SRC_SHIFT) /* internal */
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#define LPIT_TCTRL_TROT (1 << 18) /* Timer Reload On Trigger */
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#define LPIT_TCTRL_TSOI (1 << 17) /* Timer Stop On Interrupt */
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#define LPIT_TCTRL_TSOT (1 << 16) /* Timer Start On Trigger */
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#define LPIT_TCTRL_MODE_SHIFT (2)
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#define LPIT_TCTRL_MODE_MASK (3 << LPIT_TCTRL_MODE_SHIFT)
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#define LPIT_TCTRL_MODE_32PC (0 << LPIT_TCTRL_MODE_SHIFT) /* 32 Bit periodic Counter */
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#define LPIT_TCTRL_MODE_D16PC (1 << LPIT_TCTRL_MODE_SHIFT) /* Dual 16-bit periodic Counter */
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#define LPIT_TCTRL_MODE_32TA (2 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Accumulator */
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#define LPIT_TCTRL_MODE_32TIC (3 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Input Capture */
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#define LPIT_TCTRL_CHAIN (1 << 1) /* Chain Channel */
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#define LPIT_TCTRL_T_EN (1 << 0) /* Timer Enable */
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#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPIT_H */
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