2017-12-18 11:52:13 +08:00
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#
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# Topology for pass through pipeline
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#
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# Include topology builder
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2018-03-06 06:17:12 +08:00
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include(`dai.m4')
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2018-06-25 15:04:27 +08:00
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include(`ssp.m4')
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2018-06-25 15:09:53 +08:00
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include(`dmic.m4')
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2018-03-06 06:17:12 +08:00
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include(`utils.m4')
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include(`pipeline.m4')
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2017-12-18 11:52:13 +08:00
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include Baytrail DSP configuration
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2018-06-25 14:42:07 +08:00
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include(`byt.m4')
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2017-12-18 11:52:13 +08:00
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#
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# Machine Specific Config - !! MUST BE SET TO MATCH TEST MACHINE DRIVER !!
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#
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# TEST_PIPE_NAME - Pipe name
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# TEST_DAI_LINK_NAME - BE DAI link name e.g. "NoCodec"
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2018-06-01 01:34:42 +08:00
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# TEST_DAI_PORT - SSP port number e.g. 2
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# TEST_DAI_FORMAT - SSP data format e.g s16le
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2017-12-18 11:52:13 +08:00
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# TEST_PIPE_FORMAT - Pipeline format e.g. s16le
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2017-12-25 20:42:16 +08:00
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# TEST_SSP_MCLK - SSP MCLK in Hz
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2017-12-18 11:52:13 +08:00
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# TEST_SSP_BCLK - SSP BCLK in Hz
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# TEST_SSP_PHY_BITS - SSP physical slot size
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# TEST_SSP_DATA_BITS - SSP data slot size
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2018-03-30 14:57:37 +08:00
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# TEST_SSP_MODE - SSP mode e.g. I2S, LEFT_J, DSP_A and DSP_B
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2017-12-18 11:52:13 +08:00
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#
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#
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# Define the pipeline
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#
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2018-06-01 01:34:42 +08:00
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# PCM0 <---> SSP TEST_DAI_PORT
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2017-12-18 11:52:13 +08:00
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#
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2018-06-28 19:39:36 +08:00
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# Passthrough capture pipeline 2 on PCM 0 using max 4 channels.
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2017-12-18 11:52:13 +08:00
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_DAI_ADD(sof/pipe-TEST_PIPE_NAME-capture.m4,
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2018-06-28 19:39:36 +08:00
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2, 0, 4, TEST_PIPE_FORMAT,
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2018-06-13 04:01:56 +08:00
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48, 1000, 0, 0,
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2018-06-01 01:34:42 +08:00
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TEST_DAI_TYPE, TEST_DAI_PORT, TEST_DAI_FORMAT, 2)
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2017-12-18 11:52:13 +08:00
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#
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# DAI configuration
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#
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2018-06-01 01:34:42 +08:00
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# SSP port TEST_DAI_PORT is our only pipeline DAI
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2017-12-18 11:52:13 +08:00
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#
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2018-06-01 01:34:42 +08:00
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# capture DAI is SSP TEST_DAI_PORT using 2 periods
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2017-12-18 11:52:13 +08:00
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-capture.m4,
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2018-06-01 01:34:42 +08:00
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2, TEST_DAI_TYPE, TEST_DAI_PORT, TEST_DAI_LINK_NAME,
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PIPELINE_SINK_2, 2, TEST_DAI_FORMAT,
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2017-12-18 11:52:13 +08:00
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48, 1000, 0, 0)
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# PCM Passthrough
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2018-07-24 13:47:48 +08:00
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PCM_CAPTURE_ADD(Passthrough, 0, PIPELINE_PCM_2)
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2017-12-18 11:52:13 +08:00
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#
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# BE configurations - overrides config in ACPI if present
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#
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# Clocks masters wrt codec
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#
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2018-06-01 01:34:42 +08:00
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# TEST_SSP_DATA_BITS bit I2S using TEST_SSP_PHY_BITS bit sample conatiner on SSP TEST_DAI_PORT
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2017-12-18 11:52:13 +08:00
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#
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2018-06-25 17:32:43 +08:00
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DAI_CONFIG(TEST_DAI_TYPE, TEST_DAI_PORT, TEST_DAI_PORT, TEST_DAI_LINK_NAME,
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2018-06-01 01:34:48 +08:00
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ifelse(TEST_DAI_TYPE, `SSP',
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SSP_CONFIG(TEST_SSP_MODE,
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2018-06-25 15:04:27 +08:00
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SSP_CLOCK(mclk, TEST_SSP_MCLK, codec_mclk_in),
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SSP_CLOCK(bclk, TEST_SSP_BCLK, codec_slave),
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SSP_CLOCK(fsync, 48000, codec_slave),
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SSP_TDM(2, TEST_SSP_PHY_BITS, 3, 3),
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2018-06-25 13:03:16 +08:00
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SSP_CONFIG_DATA(TEST_DAI_TYPE, TEST_DAI_PORT,
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2018-06-27 01:30:12 +08:00
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TEST_SSP_DATA_BITS, TEST_SSP_MCLK_ID)),
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2018-06-01 01:34:48 +08:00
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TEST_DAI_TYPE, `DMIC',
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2018-06-26 13:17:03 +08:00
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DMIC_CONFIG(TEST_DMIC_DRIVER_VERSION, TEST_DMIC_CLK_MIN,
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2018-06-01 01:34:48 +08:00
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TEST_DMIC_CLK_MAX, TEST_DMIC_DUTY_MIN,
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2018-06-26 13:17:03 +08:00
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TEST_DMIC_DUTY_MAX, TEST_DMIC_SAMPLE_RATE,
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DMIC_WORD_LENGTH(TEST_DAI_FORMAT),
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2018-06-01 01:34:48 +08:00
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TEST_DAI_TYPE, TEST_DAI_PORT,
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PDM_CONFIG(TEST_DAI_TYPE, TEST_DAI_PORT,
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2018-06-26 13:17:03 +08:00
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TEST_DMIC_PDM_CONFIG)),
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2018-06-01 01:34:48 +08:00
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`'))
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